Lines Matching +full:0 +full:xbc
26 #define TPM_TIS_ADDR_BASE 0xFED40000
27 #define TPM_TIS_ADDR_SIZE 0x5000
35 #define TPM_TIS_REG_ACCESS 0x00
36 #define TPM_TIS_REG_INT_ENABLE 0x08
37 #define TPM_TIS_REG_INT_VECTOR 0x0c
38 #define TPM_TIS_REG_INT_STATUS 0x10
39 #define TPM_TIS_REG_INTF_CAPABILITY 0x14
40 #define TPM_TIS_REG_STS 0x18
41 #define TPM_TIS_REG_DATA_FIFO 0x24
42 #define TPM_TIS_REG_INTERFACE_ID 0x30
43 #define TPM_TIS_REG_DATA_XFIFO 0x80
44 #define TPM_TIS_REG_DATA_XFIFO_END 0xbc
45 #define TPM_TIS_REG_DID_VID 0xf00
46 #define TPM_TIS_REG_RID 0xf04
49 #define TPM_TIS_REG_DEBUG 0xf90
51 #define TPM_TIS_STS_TPM_FAMILY_MASK (0x3 << 26)/* TPM 2.0 */
52 #define TPM_TIS_STS_TPM_FAMILY1_2 (0 << 26) /* TPM 2.0 */
75 #define TPM_TIS_ACCESS_TPM_ESTABLISHMENT (1 << 0)
78 #define TPM_TIS_INT_DATA_AVAILABLE (1 << 0)
94 #define TPM_TIS_CAP_DATA_TRANSFER_LEGACY (0 << 9)
95 #define TPM_TIS_CAP_BURST_COUNT_DYNAMIC (0 << 8)
112 #define TPM_TIS_IFACE_ID_INTERFACE_TIS1_3 (0xf) /* TPM 2.0 */
113 #define TPM_TIS_IFACE_ID_INTERFACE_FIFO (0x0) /* TPM 2.0 */
114 #define TPM_TIS_IFACE_ID_INTERFACE_VER_FIFO (0 << 4) /* TPM 2.0 */
121 (~0u << 4)/* all of it is don't care */)
130 #define TPM_TIS_TPM_DID 0x0001
132 #define TPM_TIS_TPM_RID 0x0001
134 #define TPM_TIS_NO_DATA_BYTE 0xff
137 REG32(CRB_LOC_STATE, 0x00)
138 FIELD(CRB_LOC_STATE, tpmEstablished, 0, 1)
143 REG32(CRB_LOC_CTRL, 0x08)
144 REG32(CRB_LOC_STS, 0x0C)
145 FIELD(CRB_LOC_STS, Granted, 0, 1)
147 REG32(CRB_INTF_ID, 0x30)
148 FIELD(CRB_INTF_ID, InterfaceType, 0, 4)
161 REG32(CRB_INTF_ID2, 0x34)
162 FIELD(CRB_INTF_ID2, VID, 0, 16)
164 REG32(CRB_CTRL_EXT, 0x38)
165 REG32(CRB_CTRL_REQ, 0x40)
166 REG32(CRB_CTRL_STS, 0x44)
167 FIELD(CRB_CTRL_STS, tpmSts, 0, 1)
169 REG32(CRB_CTRL_CANCEL, 0x48)
170 REG32(CRB_CTRL_START, 0x4C)
171 REG32(CRB_INT_ENABLED, 0x50)
172 REG32(CRB_INT_STS, 0x54)
173 REG32(CRB_CTRL_CMD_SIZE, 0x58)
174 REG32(CRB_CTRL_CMD_LADDR, 0x5C)
175 REG32(CRB_CTRL_CMD_HADDR, 0x60)
176 REG32(CRB_CTRL_RSP_SIZE, 0x64)
177 REG32(CRB_CTRL_RSP_ADDR, 0x68)
178 REG32(CRB_DATA_BUFFER, 0x80)
180 #define TPM_CRB_ADDR_BASE 0xFED40000
181 #define TPM_CRB_ADDR_SIZE 0x1000
187 #define TPM_TCPA_ACPI_CLASS_CLIENT 0
190 #define TPM2_ACPI_CLASS_CLIENT 0
199 #define TPM_PPI_ADDR_SIZE 0x400
200 #define TPM_PPI_ADDR_BASE 0xFED45000
202 #define TPM_PPI_VERSION_NONE 0
205 /* whether function is blocked by BIOS settings; bits 0, 1, 2 */
206 #define TPM_PPI_FUNC_NOT_IMPLEMENTED (0 << 0)
207 #define TPM_PPI_FUNC_BIOS_ONLY (1 << 0)
208 #define TPM_PPI_FUNC_BLOCKED (2 << 0)
209 #define TPM_PPI_FUNC_ALLOWED_USR_REQ (3 << 0)
210 #define TPM_PPI_FUNC_ALLOWED_USR_NOT_REQ (4 << 0)
211 #define TPM_PPI_FUNC_MASK (7 << 0)
214 #define TPM_I2C_REG_LOC_SEL 0x00
215 #define TPM_I2C_REG_ACCESS 0x04
216 #define TPM_I2C_REG_INT_ENABLE 0x08
217 #define TPM_I2C_REG_INT_CAPABILITY 0x14
218 #define TPM_I2C_REG_STS 0x18
219 #define TPM_I2C_REG_DATA_FIFO 0x24
220 #define TPM_I2C_REG_INTF_CAPABILITY 0x30
221 #define TPM_I2C_REG_I2C_DEV_ADDRESS 0x38
222 #define TPM_I2C_REG_DATA_CSUM_ENABLE 0x40
223 #define TPM_I2C_REG_DATA_CSUM_GET 0x44
224 #define TPM_I2C_REG_DID_VID 0x48
225 #define TPM_I2C_REG_RID 0x4c
226 #define TPM_I2C_REG_UNKNOWN 0xff
229 #define TPM_I2C_CAP_INTERFACE_TYPE (0x2 << 0) /* FIFO interface */
230 #define TPM_I2C_CAP_INTERFACE_VER (0x0 << 4) /* TCG I2C intf 1.0 */
231 #define TPM_I2C_CAP_TPM2_FAMILY (0x1 << 7) /* TPM 2.0 family. */
232 #define TPM_I2C_CAP_DEV_ADDR_CHANGE (0x0 << 27) /* No dev addr chng */
233 #define TPM_I2C_CAP_BURST_COUNT_STATIC (0x1 << 29) /* Burst count static */
234 #define TPM_I2C_CAP_LOCALITY_CAP (0x1 << 25) /* 0-5 locality */
241 #define TPM_I2C_STS_READ_MASK 0x00ffffdd
242 #define TPM_I2C_STS_WRITE_MASK 0x03000062
245 #define TPM_DATA_CSUM_ENABLED 0x1
249 * interrupts hence setting it to 0.
251 #define TPM_I2C_INT_ENABLE_MASK 0x0