2063 static USBPort *xhci_lookup_uport(XHCIState *xhci, uint32_t *slot_ctx)  in xhci_lookup_uport()  argument
2069     port = (slot_ctx[1]>>16) & 0xFF;  in xhci_lookup_uport()
2076         port = (slot_ctx[0] >> 4*i) & 0x0f;  in xhci_lookup_uport()
2100     uint32_t slot_ctx[4];  in xhci_address_slot()  local
2123     xhci_dma_read_u32s(xhci, ictx+32, slot_ctx, sizeof(slot_ctx));  in xhci_address_slot()
2127             slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);  in xhci_address_slot()
2132     uport = xhci_lookup_uport(xhci, slot_ctx);  in xhci_address_slot()
2159     slot->intr = get_field(slot_ctx[2], TRB_INTR);  in xhci_address_slot()
2164         slot_ctx[3] = SLOT_DEFAULT << SLOT_STATE_SHIFT;  in xhci_address_slot()
2169         slot_ctx[3] = (SLOT_ADDRESSED << SLOT_STATE_SHIFT) | slotid;  in xhci_address_slot()
2185             slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);  in xhci_address_slot()
2189     xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));  in xhci_address_slot()
2202     uint32_t slot_ctx[4];  in xhci_configure_slot()  local
2224         xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));  in xhci_configure_slot()
2225         slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT);  in xhci_configure_slot()
2226         slot_ctx[3] |= SLOT_ADDRESSED << SLOT_STATE_SHIFT;  in xhci_configure_slot()
2228                 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);  in xhci_configure_slot()
2229         xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));  in xhci_configure_slot()
2243     xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));  in xhci_configure_slot()
2245     if (SLOT_STATE(slot_ctx[3]) < SLOT_ADDRESSED) {  in xhci_configure_slot()
2246         DPRINTF("xhci: invalid slot state %08x\n", slot_ctx[3]);  in xhci_configure_slot()
2283     slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT);  in xhci_configure_slot()
2284     slot_ctx[3] |= SLOT_CONFIGURED << SLOT_STATE_SHIFT;  in xhci_configure_slot()
2285     slot_ctx[0] &= ~(SLOT_CONTEXT_ENTRIES_MASK << SLOT_CONTEXT_ENTRIES_SHIFT);  in xhci_configure_slot()
2286     slot_ctx[0] |= islot_ctx[0] & (SLOT_CONTEXT_ENTRIES_MASK <<  in xhci_configure_slot()
2289             slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);  in xhci_configure_slot()
2291     xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));  in xhci_configure_slot()
2305     uint32_t slot_ctx[4];  in xhci_evaluate_slot()  local
2330         xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));  in xhci_evaluate_slot()
2332         slot_ctx[1] &= ~0xFFFF; /* max exit latency */  in xhci_evaluate_slot()
2333         slot_ctx[1] |= islot_ctx[1] & 0xFFFF;  in xhci_evaluate_slot()
2336         set_field(&slot_ctx[2], xhci->slots[slotid-1].intr, TRB_INTR);  in xhci_evaluate_slot()
2339                 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);  in xhci_evaluate_slot()
2341         xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));  in xhci_evaluate_slot()
2367     uint32_t slot_ctx[4];  in xhci_reset_slot()  local
2384     xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));  in xhci_reset_slot()
2385     slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT);  in xhci_reset_slot()
2386     slot_ctx[3] |= SLOT_DEFAULT << SLOT_STATE_SHIFT;  in xhci_reset_slot()
2388             slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);  in xhci_reset_slot()
2389     xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));  in xhci_reset_slot()
3476     uint32_t slot_ctx[4];  in usb_xhci_post_load()  local
3491         xhci_dma_read_u32s(xhci, slot->ctx, slot_ctx, sizeof(slot_ctx));  in usb_xhci_post_load()
3492         slot->uport = xhci_lookup_uport(xhci, slot_ctx);  in usb_xhci_post_load()