19 #include "hw/qdev-properties.h"
20 #include "hw/usb/hcd-ehci.h"
24     .name        = "ehci-sysbus",
35     DEFINE_PROP_BOOL("companion-enable", EHCISysBusState, ehci.companion_enable,
43     EHCIState *s = &i->ehci;  in usb_ehci_sysbus_realize()
46     sysbus_init_irq(d, &s->irq);  in usb_ehci_sysbus_realize()
53     EHCIState *s = &i->ehci;  in usb_ehci_sysbus_reset()
63     EHCIState *s = &i->ehci;  in ehci_sysbus_init()
65     s->capsbase = sec->capsbase;  in ehci_sysbus_init()
66     s->opregbase = sec->opregbase;  in ehci_sysbus_init()
67     s->portscbase = sec->portscbase;  in ehci_sysbus_init()
68     s->portnr = sec->portnr;  in ehci_sysbus_init()
69     s->as = &address_space_memory;  in ehci_sysbus_init()
72     sysbus_init_mmio(d, &s->mem);  in ehci_sysbus_init()
78     EHCIState *s = &i->ehci;  in ehci_sysbus_finalize()
88     sec->portscbase = 0x44;  in ehci_sysbus_class_init()
89     sec->portnr = EHCI_PORTS;  in ehci_sysbus_class_init()
91     dc->realize = usb_ehci_sysbus_realize;  in ehci_sysbus_class_init()
92     dc->vmsd = &vmstate_ehci_sysbus;  in ehci_sysbus_class_init()
95     set_bit(DEVICE_CATEGORY_USB, dc->categories);  in ehci_sysbus_class_init()
103     sec->capsbase = 0x0;  in ehci_platform_class_init()
104     sec->opregbase = 0x20;  in ehci_platform_class_init()
105     set_bit(DEVICE_CATEGORY_USB, dc->categories);  in ehci_platform_class_init()
113     sec->capsbase = 0x0;  in ehci_exynos4210_class_init()
114     sec->opregbase = 0x10;  in ehci_exynos4210_class_init()
115     set_bit(DEVICE_CATEGORY_USB, dc->categories);  in ehci_exynos4210_class_init()
123     sec->capsbase = 0x0;  in ehci_aw_h3_class_init()
124     sec->opregbase = 0x10;  in ehci_aw_h3_class_init()
125     set_bit(DEVICE_CATEGORY_USB, dc->categories);  in ehci_aw_h3_class_init()
133     sec->capsbase = 0x0;  in ehci_npcm7xx_class_init()
134     sec->opregbase = 0x10;  in ehci_npcm7xx_class_init()
135     sec->portscbase = 0x44;  in ehci_npcm7xx_class_init()
136     sec->portnr = 1;  in ehci_npcm7xx_class_init()
137     set_bit(DEVICE_CATEGORY_USB, dc->categories);  in ehci_npcm7xx_class_init()
145     sec->capsbase = 0x100;  in ehci_tegra2_class_init()
146     sec->opregbase = 0x140;  in ehci_tegra2_class_init()
147     set_bit(DEVICE_CATEGORY_USB, dc->categories);  in ehci_tegra2_class_init()
154     s->ehci.companion_enable = true;  in ehci_ppc4xx_init()
162     sec->capsbase = 0x0;  in ehci_ppc4xx_class_init()
163     sec->opregbase = 0x10;  in ehci_ppc4xx_class_init()
164     set_bit(DEVICE_CATEGORY_USB, dc->categories);  in ehci_ppc4xx_class_init()
173  * @FUSBH200_REG_EOF_ASTR: EOF/Async. Sleep Timer Register
176 enum FUSBH200EHCIRegs {
184     hwaddr off = s->opregbase + s->portscbase + 4 * s->portnr + addr;  in fusbh200_ehci_read()
190         /* High-Speed, VBUS valid, interrupt level-high active */  in fusbh200_ehci_read()
214     EHCIState *s = &i->ehci;  in fusbh200_ehci_init()
216     memory_region_init_io(&f->mem_vendor, OBJECT(f), &fusbh200_ehci_mmio_ops, s,  in fusbh200_ehci_init()
218     memory_region_add_subregion(&s->mem,  in fusbh200_ehci_init()
219                                 s->opregbase + s->portscbase + 4 * s->portnr,  in fusbh200_ehci_init()
220                                 &f->mem_vendor);  in fusbh200_ehci_init()
228     sec->capsbase = 0x0;  in fusbh200_ehci_class_init()
229     sec->opregbase = 0x10;  in fusbh200_ehci_class_init()
230     sec->portscbase = 0x20;  in fusbh200_ehci_class_init()
231     sec->portnr = 1;  in fusbh200_ehci_class_init()
232     set_bit(DEVICE_CATEGORY_USB, dc->categories);  in fusbh200_ehci_class_init()