39     pci_set_byte(&pci_conf[PCI_CLASS_PROG], 0x20);  in usb_ehci_pci_realize()
42     pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x00);  in usb_ehci_pci_realize()
43     /* pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x50); */  in usb_ehci_pci_realize()
46     pci_set_byte(&pci_conf[PCI_MIN_GNT], 0);  in usb_ehci_pci_realize()
47     pci_set_byte(&pci_conf[PCI_MAX_LAT], 0);  in usb_ehci_pci_realize()
49     /* pci_conf[0x50] = 0x01; *//* power management caps */  in usb_ehci_pci_realize()
52     pci_set_byte(&pci_conf[0x61], 0x20);  /* frame length adjustment (2.1.5) */  in usb_ehci_pci_realize()
53     pci_set_word(&pci_conf[0x62], 0x00);  /* port wake up capability (2.1.6) */  in usb_ehci_pci_realize()
55     pci_conf[0x64] = 0x00;  in usb_ehci_pci_realize()
56     pci_conf[0x65] = 0x00;  in usb_ehci_pci_realize()
57     pci_conf[0x66] = 0x00;  in usb_ehci_pci_realize()
58     pci_conf[0x67] = 0x00;  in usb_ehci_pci_realize()
59     pci_conf[0x68] = 0x01;  in usb_ehci_pci_realize()
60     pci_conf[0x69] = 0x00;  in usb_ehci_pci_realize()
61     pci_conf[0x6a] = 0x00;  in usb_ehci_pci_realize()
62     pci_conf[0x6b] = 0x00;  /* USBLEGSUP */  in usb_ehci_pci_realize()
63     pci_conf[0x6c] = 0x00;  in usb_ehci_pci_realize()
64     pci_conf[0x6d] = 0x00;  in usb_ehci_pci_realize()
65     pci_conf[0x6e] = 0x00;  in usb_ehci_pci_realize()
66     pci_conf[0x6f] = 0xc0;  /* USBLEFCTLSTS */  in usb_ehci_pci_realize()
72     pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mem);  in usb_ehci_pci_realize()
81     s->caps[0x09] = 0x68;        /* EECP */  in usb_ehci_pci_init()
83     s->capsbase = 0x00;  in usb_ehci_pci_init()
84     s->opregbase = 0x20;  in usb_ehci_pci_init()
85     s->portscbase = 0x44;  in usb_ehci_pci_init()
201         .revision  = 0x10,
206         .revision  = 0x03,
212         .revision  = 0x03,
227     for (i = 0; i < ARRAY_SIZE(ehci_pci_info); i++) {  in ehci_pci_register_types()