8  * it under the terms of the GNU General Public License version 2 or
13  * This is a model of the "System counter" which is documented in
14  * the Arm SSE-123 Example Subsystem Technical Reference Manual:
17  * The system counter is a non-stop 64-bit up-counter. It provides
18  * this count value to other devices like the SSE system timer,
20  * from a clock. Internally to the counter the count is actually
23  * The hardware has the optional feature that it supports dynamic
25  * one is used is selected via a CLKSEL input signal. Since the
27  * the HWCLKSW=0 configuration.
41 /* Registers in the control frame */
50  * Although CNTCR defines interrupt-related bits, the counter doesn't
52  * effectively a RAZ/WI bit, as are the reserved bits [31:6].
69 /* Registers in the status frame */
103      * Notify users of the count timestamp that they may  in sse_counter_notify_users()
123         /* Adjust the tick count to account for the scale factor */  in sse_counter_tick_to_time()
133      * For the moment we assume that both we and the devices  in sse_counter_register_consumer()
134      * which consume us last for the life of the simulation,  in sse_counter_register_consumer()
142     /* Return the CNTCV value for a particular timestamp (clock ns value). */  in sse_counter_for_timestamp()
153          * Scaling is enabled. The CNTSCR value is the amount added to  in sse_counter_for_timestamp()
154          * the underlying 88-bit counter for every tick of the  in sse_counter_for_timestamp()
155          * underlying clock; CNTCV is the top 64 bits of that full  in sse_counter_for_timestamp()
156          * 88-bit value. Multiplying the tick count by CNTSCR tells us  in sse_counter_for_timestamp()
157          * how much the full 88-bit counter has moved on; we then  in sse_counter_for_timestamp()
158          * divide that by 0x01000000 to find out how much the 64-bit  in sse_counter_for_timestamp()
159          * visible portion has advanced. muldiv64() gives us the  in sse_counter_for_timestamp()
160          * necessary at-least-88-bit precision for the intermediate  in sse_counter_for_timestamp()
170     /* Return the CNTCV value for the current time */  in sse_cntcv()
177      * Write one 32-bit half of the counter value; startbit is the  in sse_write_cntcv()
178      * bit position of this half in the 64-bit word, either 0 or 32.  in sse_write_cntcv()
201          * The only bit here is DBGH, indicating that the counter has been  in sse_counter_control_read()
202          * halted via the Halt-on-Debug signal. We don't implement halting  in sse_counter_control_read()
203          * debug, so the whole register always reads as zero.  in sse_counter_control_read()
255          * Although CNTCR defines interrupt-related bits, the counter doesn't  in sse_counter_control_write()
257          * effectively a RAZ/WI bit, as are the reserved bits [31:6].  in sse_counter_control_write()
258          * The documentation does not explicitly say so, but we assume  in sse_counter_control_write()
259          * that changing the scale factor while the counter is enabled  in sse_counter_control_write()
260          * by toggling CNTCR.SCEN has the same behaviour (making the counter  in sse_counter_control_write()
267              * Whether the counter is being enabled or disabled, the  in sse_counter_control_write()
268              * required action is the same: sync the (ns_then, ticks_then)  in sse_counter_control_write()
287          * If the scale registers are changed when the counter is enabled,  in sse_counter_control_write()
288          * the count value becomes UNKNOWN. So we don't try to recalculate  in sse_counter_control_write()
396          * Before the clock period updates, set (ticks_then, ns_then)  in sse_clk_callback()
397          * to the current time and tick count (as calculated with  in sse_clk_callback()
398          * the old clock period).  in sse_clk_callback()