82     HPETTimer timer[HPET_MAX_TIMERS];  member
97 static uint32_t timer_int_route(struct HPETTimer *timer)  in timer_int_route()  argument
99     return (timer->config & HPET_TN_INT_ROUTE_MASK) >> HPET_TN_INT_ROUTE_SHIFT;  in timer_int_route()
187 static void update_irq(struct HPETTimer *timer, int set)  in update_irq()  argument
193     if (timer->tn <= 1 && hpet_in_legacy_mode(timer->state)) {  in update_irq()
198         route = (timer->tn == 0) ? 0 : RTC_ISA_IRQ;  in update_irq()
200         route = timer_int_route(timer);  in update_irq()
202     s = timer->state;  in update_irq()
203     mask = 1 << timer->tn;  in update_irq()
205     if (set && (timer->config & HPET_TN_TYPE_LEVEL)) {  in update_irq()
215     if (set && timer_enabled(timer) && hpet_enabled(s)) {  in update_irq()
216         if (timer_fsb_route(timer)) {  in update_irq()
217             address_space_stl_le(&address_space_memory, timer->fsb >> 32,  in update_irq()
218                                  timer->fsb & 0xffffffff, MEMTXATTRS_UNSPECIFIED,  in update_irq()
220         } else if (timer->config & HPET_TN_TYPE_LEVEL) {  in update_irq()
226         if (!timer_fsb_route(timer)) {  in update_irq()
263         HPETTimer *t = &s->timer[i];  in hpet_post_load()
340         VMSTATE_STRUCT_VARRAY_UINT8(timer, HPETState, num_timers_save, 0,
454         HPETTimer *timer = &s->timer[timer_id];  in hpet_ram_read()  local
463             return timer->config >> shift;  in hpet_ram_read()
465             return timer->cmp >> shift;  in hpet_ram_read()
467             return timer->fsb >> shift;  in hpet_ram_read()
503                     if (timer_enabled(&s->timer[i]) && (s->isr & (1 << i))) {  in hpet_ram_write()
504                         update_irq(&s->timer[i], 1);  in hpet_ram_write()
506                     hpet_set_timer(&s->timer[i]);  in hpet_ram_write()
512                     hpet_del_timer(&s->timer[i]);  in hpet_ram_write()
532                     update_irq(&s->timer[i], 0);  in hpet_ram_write()
548         HPETTimer *timer = &s->timer[timer_id];  in hpet_ram_write()  local
558             old_val = timer->config;  in hpet_ram_write()
566                 update_irq(timer, 0);  in hpet_ram_write()
568             timer->config = new_val;  in hpet_ram_write()
571                 update_irq(timer, 1);  in hpet_ram_write()
574                 timer->cmp = (uint32_t)timer->cmp;  in hpet_ram_write()
575                 timer->period = (uint32_t)timer->period;  in hpet_ram_write()
578                 hpet_set_timer(timer);  in hpet_ram_write()
582             if (timer->config & HPET_TN_32BIT) {  in hpet_ram_write()
592             if (!timer_is_periodic(timer)  in hpet_ram_write()
593                 || (timer->config & HPET_TN_SETVAL)) {  in hpet_ram_write()
594                 timer->cmp = deposit64(timer->cmp, shift, len, value);  in hpet_ram_write()
596             if (timer_is_periodic(timer)) {  in hpet_ram_write()
597                 timer->period = deposit64(timer->period, shift, len, value);  in hpet_ram_write()
599             timer->config &= ~HPET_TN_SETVAL;  in hpet_ram_write()
601                 hpet_set_timer(timer);  in hpet_ram_write()
605             timer->fsb = deposit64(timer->fsb, shift, len, value);  in hpet_ram_write()
636         HPETTimer *timer = &s->timer[i];  in hpet_reset()  local
638         hpet_del_timer(timer);  in hpet_reset()
639         timer->cmp = ~0ULL;  in hpet_reset()
640         timer->config = HPET_TN_PERIODIC_CAP | HPET_TN_SIZE_CAP;  in hpet_reset()
642             timer->config |= HPET_TN_FSB_CAP;  in hpet_reset()
645         timer->config |=  (uint64_t)s->intcap << 32;  in hpet_reset()
646         timer->period = 0ULL;  in hpet_reset()
647         timer->wrap_flag = 0;  in hpet_reset()
692     HPETTimer *timer;  in hpet_realize()  local
720         timer = &s->timer[i];  in hpet_realize()
721         timer->qemu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, hpet_timer, timer);  in hpet_realize()
722         timer->tn = i;  in hpet_realize()
723         timer->state = s;  in hpet_realize()