Lines Matching +full:pwm +full:- +full:trigger
2 * AVR 16-bit timer
19 * <http://www.gnu.org/licenses/lgpl-2.1.html>
25 * ATmega640/V-1280/V-1281/V-2560/V-2561/V timers 1, 3, 4 and 5 are 16 bit
31 * PWM modes, GPIO, output capture pins, input compare pin
38 #include "hw/qdev-properties.h"
91 /* Timer mode values (not including PWM modes) */
97 #define CLKSRC(t16) (t16->crb & T16_CRB_CS)
98 #define MODE(t16) (((t16->crb & T16_CRB_WGM23) >> 1) | \
99 (t16->cra & T16_CRA_WGM01))
100 #define CNT(t16) VAL16(t16->cntl, t16->cnth)
101 #define OCRA(t16) VAL16(t16->ocral, t16->ocrah)
102 #define OCRB(t16) VAL16(t16->ocrbl, t16->ocrbh)
103 #define OCRC(t16) VAL16(t16->ocrcl, t16->ocrch)
104 #define ICR(t16) VAL16(t16->icrl, t16->icrh)
112 if (t16->period_ns == 0) { in avr_timer16_ns_to_ticks()
115 return t / t16->period_ns; in avr_timer16_ns_to_ticks()
121 cnt = avr_timer16_ns_to_ticks(t16, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - in avr_timer16_update_cnt()
122 t16->reset_time_ns); in avr_timer16_update_cnt()
123 t16->cntl = (uint8_t)(cnt & 0xff); in avr_timer16_update_cnt()
124 t16->cnth = (uint8_t)((cnt & 0xff00) >> 8); in avr_timer16_update_cnt()
129 t16->reset_time_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - in avr_timer16_recalc_reset_time()
130 CNT(t16) * t16->period_ns; in avr_timer16_recalc_reset_time()
135 t16->cntl = 0; in avr_timer16_clock_reset()
136 t16->cnth = 0; in avr_timer16_clock_reset()
137 t16->reset_time_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); in avr_timer16_clock_reset()
170 t16->freq_hz = t16->cpu_freq_hz / divider; in avr_timer16_clksrc_update()
171 t16->period_ns = NANOSECONDS_PER_SECOND / t16->freq_hz; in avr_timer16_clksrc_update()
172 trace_avr_timer16_clksrc_update(t16->freq_hz, t16->period_ns, in avr_timer16_clksrc_update()
173 (uint64_t)(1e6 / t16->freq_hz)); in avr_timer16_clksrc_update()
193 (t16->imsk & T16_INT_OCA)) { in avr_timer16_set_alarm()
212 (t16->imsk & T16_INT_OCA)) { in avr_timer16_set_alarm()
218 qemu_log_mask(LOG_UNIMP, "%s: pwm modes are unsupported\n", in avr_timer16_set_alarm()
223 (t16->imsk & T16_INT_OCB)) { in avr_timer16_set_alarm()
228 (t16->imsk & T16_INT_OCC)) { in avr_timer16_set_alarm()
232 alarm_offset -= CNT(t16); in avr_timer16_set_alarm()
234 t16->next_interrupt = next_interrupt; in avr_timer16_set_alarm()
236 t16->reset_time_ns + ((CNT(t16) + alarm_offset) * t16->period_ns); in avr_timer16_set_alarm()
237 timer_mod(t16->timer, alarm_ns); in avr_timer16_set_alarm()
239 trace_avr_timer16_next_alarm(alarm_offset * t16->period_ns); in avr_timer16_set_alarm()
259 if (t16->next_interrupt == OVERFLOW) { in avr_timer16_interrupt()
262 if (t16->imsk & T16_INT_TOV) { in avr_timer16_interrupt()
263 t16->ifr |= T16_INT_TOV; in avr_timer16_interrupt()
264 qemu_set_irq(t16->ovf_irq, 1); in avr_timer16_interrupt()
268 if (mode == T16_MODE_CTC_OCRA && t16->next_interrupt == COMPA) { in avr_timer16_interrupt()
273 if (mode == T16_MODE_CTC_ICR && t16->next_interrupt == CAPT) { in avr_timer16_interrupt()
276 if (t16->imsk & T16_INT_IC) { in avr_timer16_interrupt()
277 t16->ifr |= T16_INT_IC; in avr_timer16_interrupt()
278 qemu_set_irq(t16->capt_irq, 1); in avr_timer16_interrupt()
282 if (t16->imsk & T16_INT_OCA && t16->next_interrupt == COMPA) { in avr_timer16_interrupt()
283 t16->ifr |= T16_INT_OCA; in avr_timer16_interrupt()
284 qemu_set_irq(t16->compa_irq, 1); in avr_timer16_interrupt()
286 if (t16->imsk & T16_INT_OCB && t16->next_interrupt == COMPB) { in avr_timer16_interrupt()
287 t16->ifr |= T16_INT_OCB; in avr_timer16_interrupt()
288 qemu_set_irq(t16->compb_irq, 1); in avr_timer16_interrupt()
290 if (t16->imsk & T16_INT_OCC && t16->next_interrupt == COMPC) { in avr_timer16_interrupt()
291 t16->ifr |= T16_INT_OCC; in avr_timer16_interrupt()
292 qemu_set_irq(t16->compc_irq, 1); in avr_timer16_interrupt()
305 qemu_set_irq(t16->capt_irq, 0); in avr_timer16_reset()
306 qemu_set_irq(t16->compa_irq, 0); in avr_timer16_reset()
307 qemu_set_irq(t16->compb_irq, 0); in avr_timer16_reset()
308 qemu_set_irq(t16->compc_irq, 0); in avr_timer16_reset()
309 qemu_set_irq(t16->ovf_irq, 0); in avr_timer16_reset()
320 retval = t16->cra; in avr_timer16_read()
323 retval = t16->crb; in avr_timer16_read()
326 retval = t16->crc; in avr_timer16_read()
330 t16->rtmp = t16->cnth; in avr_timer16_read()
331 retval = t16->cntl; in avr_timer16_read()
334 retval = t16->rtmp; in avr_timer16_read()
343 t16->rtmp = t16->icrh; in avr_timer16_read()
344 retval = t16->icrl; in avr_timer16_read()
347 retval = t16->rtmp; in avr_timer16_read()
350 retval = t16->ocral; in avr_timer16_read()
353 retval = t16->ocrah; in avr_timer16_read()
356 retval = t16->ocrbl; in avr_timer16_read()
359 retval = t16->ocrbh; in avr_timer16_read()
362 retval = t16->ocrcl; in avr_timer16_read()
365 retval = t16->ocrch; in avr_timer16_read()
387 t16->cra = val8; in avr_timer16_write()
388 if (t16->cra & T16_CRA_OC_CONF) { in avr_timer16_write()
394 t16->crb = val8; in avr_timer16_write()
395 if (t16->crb & T16_CRB_ICNC) { in avr_timer16_write()
400 if (t16->crb & T16_CRB_ICES) { in avr_timer16_write()
407 t16->reset_time_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); in avr_timer16_write()
412 t16->crc = val8; in avr_timer16_write()
418 * CNT is the 16-bit counter value, it must be read/written via in avr_timer16_write()
427 t16->cntl = val8; in avr_timer16_write()
428 t16->cnth = t16->rtmp; in avr_timer16_write()
432 t16->rtmp = val8; in avr_timer16_write()
437 t16->icrl = val8; in avr_timer16_write()
438 t16->icrh = t16->rtmp; in avr_timer16_write()
443 t16->rtmp = val8; in avr_timer16_write()
449 * trigger an interrupt, when CNT is equal to the value here in avr_timer16_write()
451 t16->ocral = val8; in avr_timer16_write()
454 t16->ocrah = val8; in avr_timer16_write()
457 t16->ocrbl = val8; in avr_timer16_write()
460 t16->ocrbh = val8; in avr_timer16_write()
463 t16->ocrcl = val8; in avr_timer16_write()
466 t16->ocrch = val8; in avr_timer16_write()
480 trace_avr_timer16_read_imsk(offset ? 0 : t16->imsk); in avr_timer16_imsk_read()
484 return t16->imsk; in avr_timer16_imsk_read()
496 t16->imsk = (uint8_t)val64; in avr_timer16_imsk_write()
505 trace_avr_timer16_read_ifr(offset ? 0 : t16->ifr); in avr_timer16_ifr_read()
509 return t16->ifr; in avr_timer16_ifr_read()
521 t16->ifr = (uint8_t)val64; in avr_timer16_ifr_write()
547 DEFINE_PROP_UINT64("cpu-frequency-hz", struct AVRTimer16State,
555 s->enabled = !level; in avr_timer16_pr()
557 if (!s->enabled) { in avr_timer16_pr()
566 sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->capt_irq); in avr_timer16_init()
567 sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->compa_irq); in avr_timer16_init()
568 sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->compb_irq); in avr_timer16_init()
569 sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->compc_irq); in avr_timer16_init()
570 sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->ovf_irq); in avr_timer16_init()
572 memory_region_init_io(&s->iomem, obj, &avr_timer16_ops, in avr_timer16_init()
573 s, "avr-timer16", 0xe); in avr_timer16_init()
574 memory_region_init_io(&s->imsk_iomem, obj, &avr_timer16_imsk_ops, in avr_timer16_init()
575 s, "avr-timer16-intmask", 0x1); in avr_timer16_init()
576 memory_region_init_io(&s->ifr_iomem, obj, &avr_timer16_ifr_ops, in avr_timer16_init()
577 s, "avr-timer16-intflag", 0x1); in avr_timer16_init()
579 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem); in avr_timer16_init()
580 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->imsk_iomem); in avr_timer16_init()
581 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->ifr_iomem); in avr_timer16_init()
589 if (s->cpu_freq_hz == 0) { in avr_timer16_realize()
590 error_setg(errp, "AVR timer16: cpu-frequency-hz property must be set"); in avr_timer16_realize()
594 s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, avr_timer16_interrupt, s); in avr_timer16_realize()
595 s->enabled = true; in avr_timer16_realize()
603 dc->realize = avr_timer16_realize; in avr_timer16_class_init()