Lines Matching +full:value +full:- +full:start
9 * the COPYING file in the top-level directory.
22 #include "hw/qdev-properties.h"
28 #define TIMER_CTRL_MASK ((1 << TIMER_CTRL_BITS) - 1)
49 * Minimum value of the reload register to filter out short period
64 const AspeedTimer (*timers)[] = (void *)t - (t->id * sizeof(*t)); in timer_to_ctrl()
70 return !!(timer_to_ctrl(t)->ctrl & BIT(t->id * TIMER_CTRL_BITS + op)); in timer_ctrl_status()
85 return t->id >= TIMER_FIRST_CAP_PULSE; in timer_can_pulse()
98 aspeed_scu_get_apb_freq(s->scu); in calculate_rate()
103 uint64_t delta_ns = now_ns - MIN(now_ns, t->start); in calculate_ticks()
107 return t->reload - MIN(t->reload, ticks); in calculate_ticks()
110 static uint32_t calculate_min_ticks(AspeedTimer *t, uint32_t value) in calculate_min_ticks() argument
115 return value < min_ticks ? min_ticks : value; in calculate_min_ticks()
123 delta_ticks = t->reload - MIN(t->reload, ticks); in calculate_time()
126 return t->start + delta_ns; in calculate_time()
131 return t->match[i] < t->reload ? t->match[i] : 0; in calculate_match()
161 timer_del(&t->timer); in calculate_next()
165 t->level = !t->level; in calculate_next()
166 s->irq_sts |= BIT(t->id); in calculate_next()
167 qemu_set_irq(t->irq, t->level); in calculate_next()
171 t->start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); in calculate_next()
180 timer_mod(&t->timer, next); in aspeed_timer_mod()
197 interrupt = timer_overflow_interrupt(t) || !t->match[0] || !t->match[1]; in aspeed_timer_expire()
198 } else if (ticks <= MIN(t->match[0], t->match[1])) { in aspeed_timer_expire()
200 } else if (ticks <= MAX(t->match[0], t->match[1])) { in aspeed_timer_expire()
206 t->level = !t->level; in aspeed_timer_expire()
207 s->irq_sts |= BIT(t->id); in aspeed_timer_expire()
208 qemu_set_irq(t->irq, t->level); in aspeed_timer_expire()
216 uint64_t value; in aspeed_timer_get_value() local
221 value = calculate_ticks(t, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); in aspeed_timer_get_value()
223 value = t->reload; in aspeed_timer_get_value()
227 value = t->reload; in aspeed_timer_get_value()
231 value = t->match[reg - 2]; in aspeed_timer_get_value()
236 value = 0; in aspeed_timer_get_value()
239 return value; in aspeed_timer_get_value()
245 uint64_t value; in aspeed_timer_read_common() local
249 value = s->ctrl; in aspeed_timer_read_common()
251 case 0x00 ... 0x2c: /* Timers 1 - 4 */ in aspeed_timer_read_common()
252 value = aspeed_timer_get_value(&s->timers[(offset >> 4)], reg); in aspeed_timer_read_common()
254 case 0x40 ... 0x8c: /* Timers 5 - 8 */ in aspeed_timer_read_common()
255 value = aspeed_timer_get_value(&s->timers[(offset >> 4) - 1], reg); in aspeed_timer_read_common()
260 value = 0; in aspeed_timer_read_common()
263 return value; in aspeed_timer_read_common()
267 uint32_t value) in aspeed_timer_set_value() argument
272 trace_aspeed_timer_set_value(timer, reg, value); in aspeed_timer_set_value()
273 t = &s->timers[timer]; in aspeed_timer_set_value()
276 old_reload = t->reload; in aspeed_timer_set_value()
277 t->reload = calculate_min_ticks(t, value); in aspeed_timer_set_value()
280 * If the reload value was not previously set, or zero, and in aspeed_timer_set_value()
281 * the current value is valid, try to start the timer if it is in aspeed_timer_set_value()
284 if (old_reload || !t->reload) { in aspeed_timer_set_value()
287 /* fall through to re-enable */ in aspeed_timer_set_value()
291 int64_t delta = (int64_t) value - (int64_t) calculate_ticks(t, now); in aspeed_timer_set_value()
295 t->start += muldiv64(delta, NANOSECONDS_PER_SECOND, rate); in aspeed_timer_set_value()
297 t->start -= muldiv64(-delta, NANOSECONDS_PER_SECOND, rate); in aspeed_timer_set_value()
304 t->match[reg - 2] = value; in aspeed_timer_set_value()
324 trace_aspeed_timer_ctrl_enable(t->id, enable); in aspeed_timer_ctrl_enable()
326 t->start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); in aspeed_timer_ctrl_enable()
329 timer_del(&t->timer); in aspeed_timer_ctrl_enable()
335 trace_aspeed_timer_ctrl_external_clock(t->id, enable); in aspeed_timer_ctrl_external_clock()
340 trace_aspeed_timer_ctrl_overflow_interrupt(t->id, enable); in aspeed_timer_ctrl_overflow_interrupt()
346 trace_aspeed_timer_ctrl_pulse_enable(t->id, enable); in aspeed_timer_ctrl_pulse_enable()
403 * configuration bits - i.e. if more than one bit in the control set has in aspeed_timer_set_ctrl()
409 t = &s->timers[i]; in aspeed_timer_set_ctrl()
411 t_old = (s->ctrl >> shift) & TIMER_CTRL_MASK; in aspeed_timer_set_ctrl()
426 s->ctrl = reg; in aspeed_timer_set_ctrl()
429 static void aspeed_timer_set_ctrl2(AspeedTimerCtrlState *s, uint32_t value) in aspeed_timer_set_ctrl2() argument
431 trace_aspeed_timer_set_ctrl2(value); in aspeed_timer_set_ctrl2()
435 uint64_t value) in aspeed_timer_write_common() argument
437 const uint32_t tv = (uint32_t)(value & 0xFFFFFFFF); in aspeed_timer_write_common()
450 aspeed_timer_set_value(s, (offset >> TIMER_NR_REGS) - 1, reg, tv); in aspeed_timer_write_common()
462 return ASPEED_TIMER_GET_CLASS(s)->read(s, offset); in aspeed_timer_read()
465 static void aspeed_timer_write(void *opaque, hwaddr offset, uint64_t value, in aspeed_timer_write() argument
469 ASPEED_TIMER_GET_CLASS(s)->write(s, offset, value); in aspeed_timer_write()
483 uint64_t value; in aspeed_2400_timer_read() local
487 value = s->ctrl2; in aspeed_2400_timer_read()
493 value = 0; in aspeed_2400_timer_read()
496 value = aspeed_timer_read_common(s, offset); in aspeed_2400_timer_read()
499 trace_aspeed_timer_read(offset, value); in aspeed_2400_timer_read()
500 return value; in aspeed_2400_timer_read()
504 uint64_t value) in aspeed_2400_timer_write() argument
506 const uint32_t tv = (uint32_t)(value & 0xFFFFFFFF); in aspeed_2400_timer_write()
518 aspeed_timer_write_common(s, offset, value); in aspeed_2400_timer_write()
525 uint64_t value; in aspeed_2500_timer_read() local
529 value = s->ctrl2; in aspeed_2500_timer_read()
532 value = s->ctrl3 & BIT(0); in aspeed_2500_timer_read()
537 value = 0; in aspeed_2500_timer_read()
540 value = aspeed_timer_read_common(s, offset); in aspeed_2500_timer_read()
543 trace_aspeed_timer_read(offset, value); in aspeed_2500_timer_read()
544 return value; in aspeed_2500_timer_read()
548 uint64_t value) in aspeed_2500_timer_write() argument
550 const uint32_t tv = (uint32_t)(value & 0xFFFFFFFF); in aspeed_2500_timer_write()
558 command = (value >> 1) & 0xFF; in aspeed_2500_timer_write()
560 s->ctrl3 = 0x1; in aspeed_2500_timer_write()
562 s->ctrl3 = 0x0; in aspeed_2500_timer_write()
566 if (s->ctrl3 & BIT(0)) { in aspeed_2500_timer_write()
567 aspeed_timer_set_ctrl(s, s->ctrl & ~tv); in aspeed_2500_timer_write()
572 aspeed_timer_write_common(s, offset, value); in aspeed_2500_timer_write()
579 uint64_t value; in aspeed_2600_timer_read() local
583 value = s->irq_sts; in aspeed_2600_timer_read()
589 value = 0; in aspeed_2600_timer_read()
592 value = aspeed_timer_read_common(s, offset); in aspeed_2600_timer_read()
595 trace_aspeed_timer_read(offset, value); in aspeed_2600_timer_read()
596 return value; in aspeed_2600_timer_read()
600 uint64_t value) in aspeed_2600_timer_write() argument
602 const uint32_t tv = (uint32_t)(value & 0xFFFFFFFF); in aspeed_2600_timer_write()
606 s->irq_sts &= ~tv; in aspeed_2600_timer_write()
609 aspeed_timer_set_ctrl(s, s->ctrl & ~tv); in aspeed_2600_timer_write()
616 aspeed_timer_write_common(s, offset, value); in aspeed_2600_timer_write()
636 * configuration bits - i.e. if more than one bit in the control set has in aspeed_2700_timer_set_ctrl()
642 t = &s->timers[index]; in aspeed_2700_timer_set_ctrl()
645 t_old = (s->ctrl >> shift) & TIMER_CTRL_MASK; in aspeed_2700_timer_set_ctrl()
651 s->ctrl = deposit32(s->ctrl, shift + op_external_clock, 1, 1); in aspeed_2700_timer_set_ctrl()
657 s->ctrl = deposit32(s->ctrl, shift + op_overflow_interrupt, 1, 1); in aspeed_2700_timer_set_ctrl()
664 s->ctrl = deposit32(s->ctrl, shift + op_pulse_enable, 1, 1); in aspeed_2700_timer_set_ctrl()
671 s->ctrl = deposit32(s->ctrl, shift + op_enable, 1, 1); in aspeed_2700_timer_set_ctrl()
690 * configuration bits - i.e. if more than one bit in the control set has in aspeed_2700_timer_clear_ctrl()
695 t = &s->timers[index]; in aspeed_2700_timer_clear_ctrl()
698 t_old = (s->ctrl >> shift) & TIMER_CTRL_MASK; in aspeed_2700_timer_clear_ctrl()
705 s->ctrl = deposit32(s->ctrl, shift + op_enable, 1, 0); in aspeed_2700_timer_clear_ctrl()
711 s->ctrl = deposit32(s->ctrl, shift + op_external_clock, 1, 0); in aspeed_2700_timer_clear_ctrl()
717 s->ctrl = deposit32(s->ctrl, shift + op_overflow_interrupt, 1, 0); in aspeed_2700_timer_clear_ctrl()
723 s->ctrl = deposit32(s->ctrl, shift + op_pulse_enable, 1, 0); in aspeed_2700_timer_clear_ctrl()
728 s->irq_sts = deposit32(s->irq_sts, index, 1, 0); in aspeed_2700_timer_clear_ctrl()
736 uint64_t value = 0; in aspeed_2700_timer_read() local
753 value = aspeed_timer_get_value(&s->timers[timer_index], in aspeed_2700_timer_read()
758 value = deposit64(value, 0, 4, in aspeed_2700_timer_read()
759 extract32(s->ctrl, timer_index * 4, 4)); in aspeed_2700_timer_read()
760 value = deposit64(value, 16, 1, in aspeed_2700_timer_read()
761 extract32(s->irq_sts, timer_index, 1)); in aspeed_2700_timer_read()
766 value = 0; in aspeed_2700_timer_read()
769 trace_aspeed_timer_read(offset, value); in aspeed_2700_timer_read()
770 return value; in aspeed_2700_timer_read()
774 uint64_t value) in aspeed_2700_timer_write() argument
776 const uint32_t timer_value = (uint32_t)(value & 0xFFFFFFFF); in aspeed_2700_timer_write()
814 AspeedTimer *t = &s->timers[id]; in aspeed_init_one_timer()
816 t->id = id; in aspeed_init_one_timer()
817 timer_init_ns(&t->timer, QEMU_CLOCK_VIRTUAL, aspeed_timer_expire, t); in aspeed_init_one_timer()
826 assert(s->scu); in aspeed_timer_realize()
830 sysbus_init_irq(sbd, &s->timers[i].irq); in aspeed_timer_realize()
832 memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_timer_ops, s, in aspeed_timer_realize()
834 sysbus_init_mmio(sbd, &s->iomem); in aspeed_timer_realize()
843 AspeedTimer *t = &s->timers[i]; in aspeed_timer_reset()
852 t->level = 0; in aspeed_timer_reset()
853 t->reload = 0; in aspeed_timer_reset()
854 t->match[0] = 0; in aspeed_timer_reset()
855 t->match[1] = 0; in aspeed_timer_reset()
857 s->ctrl = 0; in aspeed_timer_reset()
858 s->ctrl2 = 0; in aspeed_timer_reset()
859 s->ctrl3 = 0; in aspeed_timer_reset()
860 s->irq_sts = 0; in aspeed_timer_reset()
902 dc->realize = aspeed_timer_realize; in timer_class_init()
904 dc->desc = "ASPEED Timer"; in timer_class_init()
905 dc->vmsd = &vmstate_aspeed_timer_state; in timer_class_init()
923 dc->desc = "ASPEED 2400 Timer"; in aspeed_2400_timer_class_init()
924 awc->read = aspeed_2400_timer_read; in aspeed_2400_timer_class_init()
925 awc->write = aspeed_2400_timer_write; in aspeed_2400_timer_class_init()
939 dc->desc = "ASPEED 2500 Timer"; in aspeed_2500_timer_class_init()
940 awc->read = aspeed_2500_timer_read; in aspeed_2500_timer_class_init()
941 awc->write = aspeed_2500_timer_write; in aspeed_2500_timer_class_init()
955 dc->desc = "ASPEED 2600 Timer"; in aspeed_2600_timer_class_init()
956 awc->read = aspeed_2600_timer_read; in aspeed_2600_timer_class_init()
957 awc->write = aspeed_2600_timer_write; in aspeed_2600_timer_class_init()
971 dc->desc = "ASPEED 1030 Timer"; in aspeed_1030_timer_class_init()
972 awc->read = aspeed_2600_timer_read; in aspeed_1030_timer_class_init()
973 awc->write = aspeed_2600_timer_write; in aspeed_1030_timer_class_init()
987 dc->desc = "ASPEED 2700 Timer"; in aspeed_2700_timer_class_init()
988 awc->read = aspeed_2700_timer_read; in aspeed_2700_timer_class_init()
989 awc->write = aspeed_2700_timer_write; in aspeed_2700_timer_class_init()