44 #define DB_PRINT_L(level, ...) do { \  macro
233             DB_PRINT_L(1, "%sselecting peripheral %d\n",  in xilinx_spips_update_cs()
244         DB_PRINT_L(1, "moving to snoop check state\n");  in xilinx_spips_update_cs()
463             DB_PRINT_L(0, "GQSPI command: %x\n", s->regs[R_GQSPI_GF_SNAPSHOT]);  in xlnx_zynqmp_qspips_flush_fifo_g()
465                 DB_PRINT_L(0, "Dummy GQSPI Delay Command Entry, Do nothing");  in xlnx_zynqmp_qspips_flush_fifo_g()
523             DB_PRINT_L(1, "bus %d tx = %02x\n", i, tx_rx[i]);  in xlnx_zynqmp_qspips_flush_fifo_g()
525             DB_PRINT_L(1, "bus %d rx = %02x\n", i, tx_rx[i]);  in xlnx_zynqmp_qspips_flush_fifo_g()
536                     DB_PRINT_L(1, "bus %d push_byte = %02x\n", i, tx_rx[i]);  in xlnx_zynqmp_qspips_flush_fifo_g()
650                 DB_PRINT_L(debug_level, "tx = %02x\n", tx_rx[i]);  in xilinx_spips_flush_txfifo()
652                 DB_PRINT_L(debug_level, "rx = %02x\n", tx_rx[i]);  in xilinx_spips_flush_txfifo()
657             DB_PRINT_L(debug_level, "dircarding drained rx byte\n");  in xilinx_spips_flush_txfifo()
660             DB_PRINT_L(debug_level, "dircarding discarded rx byte\n");  in xilinx_spips_flush_txfifo()
664             DB_PRINT_L(0, "rx FIFO overflow");  in xilinx_spips_flush_txfifo()
669                 DB_PRINT_L(debug_level, "pushing striped rx byte\n");  in xilinx_spips_flush_txfifo()
672            DB_PRINT_L(debug_level, "pushing unstriped rx byte\n");  in xilinx_spips_flush_txfifo()
683         DB_PRINT_L(debug_level, "initial snoop state: %x\n",  in xilinx_spips_flush_txfifo()
733                 DB_PRINT_L(0, "squelching debug info ....\n");  in xilinx_spips_flush_txfifo()
740         DB_PRINT_L(debug_level, "final snoop state: %x\n",  in xilinx_spips_flush_txfifo()
892         DB_PRINT_L(0, "addr=" HWADDR_FMT_plx " = %x\n", addr * 4, ret);  in xilinx_spips_read()
921         DB_PRINT_L(0, "addr=" HWADDR_FMT_plx " = %x\n", addr * 4, ret);  in xilinx_spips_read()
926     DB_PRINT_L(0, "addr=" HWADDR_FMT_plx " = %x\n", addr * 4,  in xilinx_spips_read()
976     DB_PRINT_L(0, "addr=" HWADDR_FMT_plx " = %x\n", addr, (unsigned)value);  in xilinx_spips_write()
1167         DB_PRINT_L(0, "config reg status: %08x\n", s->regs[R_LQSPI_CFG]);  in lqspi_load_cache()
1173         DB_PRINT_L(0, "pushing read instruction: %02x\n",  in lqspi_load_cache()
1178         DB_PRINT_L(0, "pushing read address %06x\n", flash_addr);  in lqspi_load_cache()
1194             DB_PRINT_L(0, "pushing dummy byte\n");  in lqspi_load_cache()
1201         DB_PRINT_L(0, "starting QSPI data read\n");  in lqspi_load_cache()
1230         DB_PRINT_L(1, "addr: %08" HWADDR_PRIx ", data: %08" PRIx64 "\n",  in lqspi_read()
1275     DB_PRINT_L(0, "realized spips\n");  in xilinx_spips_realize()
1321     DB_PRINT_L(0, "realized qspips\n");  in xilinx_qspips_realize()