46     uint16_t rdr_match_mask = GETFIELD(SPI_MM_RDR_MATCH_MASK, s->regs[SPI_MM_REG]);  in does_rdr_match()
47     uint16_t rdr_match_val = GETFIELD(SPI_MM_RDR_MATCH_VAL, s->regs[SPI_MM_REG]);  in does_rdr_match()
50             GETFIELD(PPC_BITMASK(48, 63), s->regs[SPI_RCV_DATA_REG]))) {  in does_rdr_match()
137         ecc_control = GETFIELD(SPI_CLK_CFG_ECC_CTRL, s->regs[SPI_CLK_CFG_REG]);  in spi_response()
177             if (GETFIELD(SPI_STS_RDR_FULL, s->status) == 1) {  in spi_response()
259         s->N1_bits = GETFIELD(SPI_CTR_CFG_N1, s->regs[SPI_CTR_CFG_REG]);  in calculate_N1()
264         if (GETFIELD(SPI_CTR_CFG_N1_CTRL_B2, s->regs[SPI_CTR_CFG_REG]) == 1) {  in calculate_N1()
268         if (GETFIELD(SPI_CTR_CFG_N1_CTRL_B3, s->regs[SPI_CTR_CFG_REG]) == 1) {  in calculate_N1()
282         if (GETFIELD(SPI_CTR_CFG_N1_CTRL_B1, s->regs[SPI_CTR_CFG_REG]) == 1) {  in calculate_N1()
287             if (GETFIELD(SPI_CTR_CFG_N1_CTRL_B2, s->regs[SPI_CTR_CFG_REG]) == 0) {  in calculate_N1()
291             if (GETFIELD(SPI_CTR_CFG_N1_CTRL_B3, s->regs[SPI_CTR_CFG_REG]) == 1) {  in calculate_N1()
303     uint8_t ecc_control = GETFIELD(SPI_CLK_CFG_ECC_CTRL, s->regs[SPI_CLK_CFG_REG]);  in calculate_N1()
367             if (GETFIELD(SPI_STS_TDR_FULL, s->status) == 1) {  in operation_shiftn1()
404             if ((s->N1_rx != 0) && (GETFIELD(SPI_STS_RDR_FULL, s->status) == 1)) {  in operation_shiftn1()
429         (GETFIELD(SPI_STS_TDR_FULL, s->status) == 1)) {  in operation_shiftn1()
442        (GETFIELD(SPI_CTR_CFG_N2_CTRL_B0, s->regs[SPI_CTR_CFG_REG]) == 1)) {  in operation_shiftn1()
494         s->N2_bits = GETFIELD(SPI_CTR_CFG_N2, s->regs[SPI_CTR_CFG_REG]);  in calculate_N2()
499         if (GETFIELD(SPI_CTR_CFG_N2_CTRL_B2, s->regs[SPI_CTR_CFG_REG]) == 1) {  in calculate_N2()
503         if (GETFIELD(SPI_CTR_CFG_N2_CTRL_B3, s->regs[SPI_CTR_CFG_REG]) == 1) {  in calculate_N2()
514         if (GETFIELD(SPI_CTR_CFG_N2_CTRL_B1, s->regs[SPI_CTR_CFG_REG]) == 1) {  in calculate_N2()
519             if (GETFIELD(SPI_CTR_CFG_N2_CTRL_B3, s->regs[SPI_CTR_CFG_REG]) == 0) {  in calculate_N2()
523             if (GETFIELD(SPI_CTR_CFG_N2_CTRL_B2, s->regs[SPI_CTR_CFG_REG]) == 1) {  in calculate_N2()
536     uint8_t ecc_control = GETFIELD(SPI_CLK_CFG_ECC_CTRL, s->regs[SPI_CLK_CFG_REG]);  in calculate_N2()
584         if ((s->N2_rx != 0) && (GETFIELD(SPI_STS_RDR_FULL, s->status) == 1)) {  in operation_shiftn2()
624         if ((s->N2_tx != 0) && (GETFIELD(SPI_STS_TDR_FULL, s->status) == 1)) {  in operation_shiftn2()
667     if (GETFIELD(SPI_STS_SEQ_FSM, s->status) == SEQ_STATE_IDLE) {  in operation_sequencer()
674     seq_index = GETFIELD(SPI_STS_SEQ_INDEX, s->status);  in operation_sequencer()
761             if ((GETFIELD(SPI_STS_SHIFTER_FSM, s->status) == FSM_IDLE) ||  in operation_sequencer()
762                 (GETFIELD(SPI_STS_SHIFTER_FSM, s->status) == FSM_DONE)) {  in operation_sequencer()
764                               "shifter state = 0x%llx", GETFIELD(  in operation_sequencer()
803                     if (GETFIELD(SPI_STS_TDR_UNDERRUN, s->status)) {  in operation_sequencer()
831                               GETFIELD(SPI_STS_SHIFTER_FSM, s->status));  in operation_sequencer()
871             if (GETFIELD(SPI_STS_RDR_FULL, s->status) == 1) {  in operation_sequencer()
928                 GETFIELD(SPI_CTR_CFG_CMP1, s->regs[SPI_CTR_CFG_REG])) {  in operation_sequencer()
947             uint8_t condition2 = GETFIELD(SPI_CTR_CFG_CMP2,  in operation_sequencer()
1060         if (GETFIELD(SPI_STS_SHIFTER_FSM, s->status) == FSM_WAIT) {  in pnv_spi_xscom_read()
1104         if ((GETFIELD(SPI_CLK_CFG_RST_CTRL, s->regs[SPI_CLK_CFG_REG]) == 0x5)  in pnv_spi_xscom_write()
1105              && (GETFIELD(SPI_CLK_CFG_RST_CTRL, val) == 0xA)) {  in pnv_spi_xscom_write()
1136                                   GETFIELD(SPI_STS_RDR, val));  in pnv_spi_xscom_write()
1138                                   GETFIELD(SPI_STS_TDR, val));  in pnv_spi_xscom_write()