Lines Matching full:status
112 * - RDR full and RDR overrun status in spi_response()
171 * Data was received so handle RDR status. in spi_response()
172 * It is easier to handle RDR_full and RDR_overrun status here in spi_response()
174 * multiple times in a row. Controlling RDR status is done here in spi_response()
177 if (GETFIELD(SPI_STS_RDR_FULL, s->status) == 1) { in spi_response()
182 s->status = SETFIELD(SPI_STS_RDR_OVERRUN, s->status, 1); in spi_response()
185 * Set status to indicate that the received data register is in spi_response()
188 s->status = SETFIELD(SPI_STS_RDR_FULL, s->status, 1); in spi_response()
367 if (GETFIELD(SPI_STS_TDR_FULL, s->status) == 1) { in operation_shiftn1()
399 * - we are transmitting and we don't care about RDR status in operation_shiftn1()
404 if ((s->N1_rx != 0) && (GETFIELD(SPI_STS_RDR_FULL, s->status) == 1)) { in operation_shiftn1()
421 * and the TDR is full we need to clear the TDR_full status. in operation_shiftn1()
426 * was unloaded and will be shifted so we have to clear the TDR_full status. in operation_shiftn1()
429 (GETFIELD(SPI_STS_TDR_FULL, s->status) == 1)) { in operation_shiftn1()
430 s->status = SETFIELD(SPI_STS_TDR_FULL, s->status, 0); in operation_shiftn1()
446 s->status = SETFIELD(SPI_STS_TDR_UNDERRUN, s->status, 1); in operation_shiftn1()
584 if ((s->N2_rx != 0) && (GETFIELD(SPI_STS_RDR_FULL, s->status) == 1)) { in operation_shiftn2()
621 * TDR_full status. Do this here instead of up in the loop above so we in operation_shiftn2()
624 if ((s->N2_tx != 0) && (GETFIELD(SPI_STS_TDR_FULL, s->status) == 1)) { in operation_shiftn2()
625 s->status = SETFIELD(SPI_STS_TDR_FULL, s->status, 0); in operation_shiftn2()
662 s->status = SETFIELD(SPI_STS_GEN_STATUS_B3, s->status, 0); in operation_sequencer()
667 if (GETFIELD(SPI_STS_SEQ_FSM, s->status) == SEQ_STATE_IDLE) { in operation_sequencer()
668 s->status = SETFIELD(SPI_STS_SEQ_INDEX, s->status, 0); in operation_sequencer()
671 * SPI_STS_SEQ_INDEX of status register is kept in seq_index variable and in operation_sequencer()
672 * updated back to status register at the end of operation_sequencer(). in operation_sequencer()
674 seq_index = GETFIELD(SPI_STS_SEQ_INDEX, s->status); in operation_sequencer()
682 s->status = SETFIELD(SPI_STS_SEQ_FSM, s->status, SEQ_STATE_DECODE); in operation_sequencer()
695 s->status = SETFIELD(SPI_STS_SEQ_FSM, s->status, SEQ_STATE_EXECUTE); in operation_sequencer()
700 s->status = SETFIELD(SPI_STS_SHIFTER_FSM, s->status, FSM_IDLE); in operation_sequencer()
703 s->status = SETFIELD(SPI_STS_SEQ_FSM, s->status, SEQ_STATE_IDLE); in operation_sequencer()
707 s->status = SETFIELD(SPI_STS_SEQ_FSM, s->status, SEQ_STATE_EXECUTE); in operation_sequencer()
720 s->status = SETFIELD(SPI_STS_SHIFTER_FSM, s->status, FSM_DONE); in operation_sequencer()
725 s->status = SETFIELD(SPI_STS_SHIFTER_FSM, s->status, FSM_IDLE); in operation_sequencer()
732 s->status = SETFIELD(SPI_STS_SHIFTER_FSM, s->status, FSM_START); in operation_sequencer()
745 s->status = SETFIELD(SPI_STS_SEQ_FSM, s->status, in operation_sequencer()
751 s->status = SETFIELD(SPI_STS_SEQ_FSM, s->status, SEQ_STATE_EXECUTE); in operation_sequencer()
761 if ((GETFIELD(SPI_STS_SHIFTER_FSM, s->status) == FSM_IDLE) || in operation_sequencer()
762 (GETFIELD(SPI_STS_SHIFTER_FSM, s->status) == FSM_DONE)) { in operation_sequencer()
765 SPI_STS_SHIFTER_FSM, s->status)); in operation_sequencer()
768 * in status reg. in operation_sequencer()
770 s->status = SETFIELD(SPI_STS_GEN_STATUS_B3, s->status, 1); in operation_sequencer()
789 s->status = SETFIELD(SPI_STS_SHIFTER_FSM, s->status, FSM_SHIFT_N1); in operation_sequencer()
803 if (GETFIELD(SPI_STS_TDR_UNDERRUN, s->status)) { in operation_sequencer()
805 s->status = SETFIELD(SPI_STS_SHIFTER_FSM, s->status, in operation_sequencer()
813 s->status = SETFIELD(SPI_STS_SHIFTER_FSM, s->status, FSM_WAIT); in operation_sequencer()
819 s->status = SETFIELD(SPI_STS_SEQ_FSM, s->status, in operation_sequencer()
826 s->status = SETFIELD(SPI_STS_SEQ_FSM, s->status, SEQ_STATE_EXECUTE); in operation_sequencer()
831 GETFIELD(SPI_STS_SHIFTER_FSM, s->status)); in operation_sequencer()
835 * error bit 3 (general_SPI_status[3]) in status reg. in operation_sequencer()
837 s->status = SETFIELD(SPI_STS_GEN_STATUS_B3, s->status, 1); in operation_sequencer()
842 s->status = SETFIELD(SPI_STS_SHIFTER_FSM, s->status, FSM_SHIFT_N2); in operation_sequencer()
849 s->status = SETFIELD(SPI_STS_SHIFTER_FSM, s->status, FSM_WAIT); in operation_sequencer()
853 s->status = SETFIELD(SPI_STS_SEQ_FSM, s->status, in operation_sequencer()
860 s->status = SETFIELD(SPI_STS_SEQ_FSM, s->status, SEQ_STATE_EXECUTE); in operation_sequencer()
871 if (GETFIELD(SPI_STS_RDR_FULL, s->status) == 1) { in operation_sequencer()
879 s->status = SETFIELD(SPI_STS_SEQ_FSM, s->status, in operation_sequencer()
902 s->status = SETFIELD(SPI_STS_RDR_FULL, s->status, 0); in operation_sequencer()
907 s->status = SETFIELD(SPI_STS_SHIFTER_FSM, s->status, FSM_WAIT); in operation_sequencer()
912 s->status = SETFIELD(SPI_STS_SEQ_FSM, s->status, SEQ_STATE_EXECUTE); in operation_sequencer()
915 s->status = SETFIELD(SPI_STS_SEQ_FSM, s->status, SEQ_STATE_INDEX_INCREMENT); in operation_sequencer()
919 s->status = SETFIELD(SPI_STS_SEQ_FSM, s->status, SEQ_STATE_EXECUTE); in operation_sequencer()
939 s->status = SETFIELD(SPI_STS_SEQ_FSM, s->status, in operation_sequencer()
945 s->status = SETFIELD(SPI_STS_SEQ_FSM, s->status, SEQ_STATE_EXECUTE); in operation_sequencer()
966 s->status = SETFIELD(SPI_STS_SEQ_FSM, s->status, in operation_sequencer()
972 s->status = SETFIELD(SPI_STS_SEQ_FSM, s->status, SEQ_STATE_EXECUTE); in operation_sequencer()
975 s->status = SETFIELD(SPI_STS_SEQ_FSM, s->status, SEQ_STATE_INDEX_INCREMENT); in operation_sequencer()
985 s->status = SETFIELD(SPI_STS_SHIFTER_FSM, s->status, FSM_IDLE); in operation_sequencer()
989 s->status = SETFIELD(SPI_STS_SEQ_FSM, s->status, SEQ_STATE_IDLE); in operation_sequencer()
997 /* Update sequencer index field in status.*/ in operation_sequencer()
998 s->status = SETFIELD(SPI_STS_SEQ_INDEX, s->status, seq_index); in operation_sequencer()
1007 * The configuration register values are not changed. The status register is
1059 s->status = SETFIELD(SPI_STS_RDR_FULL, s->status, 0); in pnv_spi_xscom_read()
1060 if (GETFIELD(SPI_STS_SHIFTER_FSM, s->status) == FSM_WAIT) { in pnv_spi_xscom_read()
1072 val = s->status; in pnv_spi_xscom_read()
1115 * register full status bit in the status register to be set. Writing in pnv_spi_xscom_write()
1116 * when the transmit data register full status bit is already set in pnv_spi_xscom_write()
1123 s->status = SETFIELD(SPI_STS_TDR_FULL, s->status, 1); in pnv_spi_xscom_write()
1124 s->status = SETFIELD(SPI_STS_TDR_UNDERRUN, s->status, 0); in pnv_spi_xscom_write()
1135 s->status = SETFIELD(SPI_STS_RDR_OVERRUN, s->status, in pnv_spi_xscom_write()
1137 s->status = SETFIELD(SPI_STS_TDR_OVERRUN, s->status, in pnv_spi_xscom_write()