112      * - RDR full and RDR overrun status  in spi_response()
186                  * full. This flag is only cleared once the RDR is unloaded.  in spi_response()
220                 qemu_log_mask(LOG_GUEST_ERROR, "pnv_spi: RX_FIFO is full\n");  in transfer()
370                  * is full otherwise we don't touch the payload because we are  in operation_shiftn1()
381                     qemu_log_mask(LOG_GUEST_ERROR, "pnv_spi: TX_FIFO is full\n");  in operation_shiftn1()
398              *   is full so we need to stop until the RDR is read  in operation_shiftn1()
406                                 "set for receive but RDR is full");  in operation_shiftn1()
413                 qemu_log_mask(LOG_GUEST_ERROR, "pnv_spi: TX_FIFO is full\n");  in operation_shiftn1()
421      * and the TDR is full we need to clear the TDR_full status.  in operation_shiftn1()
434      * or RDR full condition with N1 set to receive.  If we haven't stopped due  in operation_shiftn1()
449      * If send_n1_alone is set AND we have a full TDR then this is the first and  in operation_shiftn1()
454         /* We have a TX and a full TDR or an RX and an empty RDR */  in operation_shiftn1()
580          * If the RDR is full and we need to RX just bail out, letting the  in operation_shiftn2()
582          * buffer since RDR full causes a sequence stop and restart.  in operation_shiftn2()
586                             "for receive but RDR is full");  in operation_shiftn2()
598                 qemu_log_mask(LOG_GUEST_ERROR, "pnv_spi: TX_FIFO is full\n");  in operation_shiftn2()
610             qemu_log_mask(LOG_GUEST_ERROR, "pnv_spi: TX_FIFO is full\n");  in operation_shiftn2()
616         /* We have a TX and a full TDR or an RX and an empty RDR */  in operation_shiftn2()
620          * If we are doing an N2 TX and the TDR is full we need to clear the  in operation_shiftn2()
794                      * (1) RDR is full and the N1 shift is set for receive  in operation_sequencer()
868              * completed and will stop the sequencer until RDR full is set to  in operation_sequencer()
905                                 "full for 0x6x opcode");  in operation_sequencer()
1115          * register full status bit in the status register to be set.  Writing  in pnv_spi_xscom_write()
1116          * when the transmit data register full status bit is already set  in pnv_spi_xscom_write()