17 #define NUM_REGISTERS   0x33
34 #define DPS310_PRS_B2           0x00
35 #define DPS310_PRS_B1           0x01
36 #define DPS310_PRS_B0           0x02
37 #define DPS310_TMP_B2           0x03
38 #define DPS310_TMP_B1           0x04
39 #define DPS310_TMP_B0           0x05
40 #define DPS310_PRS_CFG          0x06
41 #define DPS310_TMP_CFG          0x07
42 #define  DPS310_TMP_RATE_BITS   (0x70)
43 #define DPS310_MEAS_CFG         0x08
44 #define  DPS310_MEAS_CTRL_BITS  (0x07)
45 #define   DPS310_PRESSURE_EN    BIT(0)
52 #define DPS310_CFG_REG          0x09
53 #define DPS310_RESET            0x0c
54 #define  DPS310_RESET_MAGIC     (BIT(0) | BIT(3))
55 #define DPS310_COEF_BASE        0x10
56 #define DPS310_COEF_LAST        0x21
57 #define DPS310_COEF_SRC         0x28
64         0xfe, 0x2f, 0xee, 0x02, 0x69, 0xa6, 0x00, 0x80, 0xc7, 0x00, 0x00, 0x00,  in dps310_reset()
65         0x00, 0x10, 0x00, 0x00, 0x0e, 0x1e, 0xdd, 0x13, 0xca, 0x5f, 0x21, 0x52,  in dps310_reset()
66         0xf9, 0xc6, 0x04, 0xd1, 0xdb, 0x47, 0x00, 0x5b, 0xfb, 0x3a, 0x00, 0x00,  in dps310_reset()
67         0x20, 0x49, 0x4e, 0xa5, 0x90, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  in dps310_reset()
68         0x60, 0x15, 0x02  in dps310_reset()
72     s->pointer = 0;  in dps310_reset()
82         qemu_log_mask(LOG_GUEST_ERROR, "%s: register 0x%02x out of bounds\n",  in dps310_read()
84         return 0xFF;  in dps310_read()
100     case 0x32: /* Undocumented register to indicate workaround not required */  in dps310_read()
103         qemu_log_mask(LOG_UNIMP, "%s: register 0x%02x unimplemented\n",  in dps310_read()
105         return 0xFF;  in dps310_read()
130         qemu_log_mask(LOG_UNIMP, "%s: register 0x%02x unimplemented\n",  in dps310_write()
143         return 0xFF;  in dps310_rx()
151     if (s->len == 0) {  in dps310_tx()
162     return 0;  in dps310_tx()
171         s->pointer = 0xFF;  in dps310_event()
172         s->len = 0;  in dps310_event()
184     return 0;  in dps310_event()
189     .version_id = 0,
190     .minimum_version_id = 0,