Lines Matching +full:multi +full:- +full:attr
10 * Based on MMC controller for Samsung S5PC1xx-based board emulation
29 #include "qemu/error-report.h"
32 #include "hw/qdev-properties.h"
38 #include "sdhci-internal.h"
43 #define TYPE_SDHCI_BUS "sdhci-bus"
52 return 1 << (9 + FIELD_EX32(s->capareg, SDHC_CAPAB, MAXBLOCKLENGTH)); in DECLARE_INSTANCE_CHECKER()
59 if (s->sd_spec_version >= 3) { in sdhci_check_capab_freq_range()
68 "in range 0-63 only", desc); in sdhci_check_capab_freq_range()
76 uint64_t msk = s->capareg; in sdhci_check_capareg()
80 switch (s->sd_spec_version) { in sdhci_check_capareg()
82 val = FIELD_EX64(s->capareg, SDHC_CAPAB, BUS64BIT_V4); in sdhci_check_capareg()
83 trace_sdhci_capareg("64-bit system bus (v4)", val); in sdhci_check_capareg()
86 val = FIELD_EX64(s->capareg, SDHC_CAPAB, UHS_II); in sdhci_check_capareg()
87 trace_sdhci_capareg("UHS-II", val); in sdhci_check_capareg()
90 val = FIELD_EX64(s->capareg, SDHC_CAPAB, ADMA3); in sdhci_check_capareg()
96 val = FIELD_EX64(s->capareg, SDHC_CAPAB, ASYNC_INT); in sdhci_check_capareg()
100 val = FIELD_EX64(s->capareg, SDHC_CAPAB, SLOT_TYPE); in sdhci_check_capareg()
102 error_setg(errp, "slot-type not supported"); in sdhci_check_capareg()
109 val = FIELD_EX64(s->capareg, SDHC_CAPAB, EMBEDDED_8BIT); in sdhci_check_capareg()
110 trace_sdhci_capareg("8-bit bus", val); in sdhci_check_capareg()
114 val = FIELD_EX64(s->capareg, SDHC_CAPAB, BUS_SPEED); in sdhci_check_capareg()
118 val = FIELD_EX64(s->capareg, SDHC_CAPAB, DRIVER_STRENGTH); in sdhci_check_capareg()
122 val = FIELD_EX64(s->capareg, SDHC_CAPAB, TIMER_RETUNING); in sdhci_check_capareg()
123 trace_sdhci_capareg("timer re-tuning", val); in sdhci_check_capareg()
126 val = FIELD_EX64(s->capareg, SDHC_CAPAB, SDR50_TUNING); in sdhci_check_capareg()
130 val = FIELD_EX64(s->capareg, SDHC_CAPAB, RETUNING_MODE); in sdhci_check_capareg()
131 trace_sdhci_capareg("re-tuning mode", val); in sdhci_check_capareg()
134 val = FIELD_EX64(s->capareg, SDHC_CAPAB, CLOCK_MULT); in sdhci_check_capareg()
140 val = FIELD_EX64(s->capareg, SDHC_CAPAB, ADMA2); in sdhci_check_capareg()
144 val = FIELD_EX64(s->capareg, SDHC_CAPAB, ADMA1); in sdhci_check_capareg()
148 val = FIELD_EX64(s->capareg, SDHC_CAPAB, BUS64BIT); in sdhci_check_capareg()
149 trace_sdhci_capareg("64-bit system bus (v3)", val); in sdhci_check_capareg()
154 y = FIELD_EX64(s->capareg, SDHC_CAPAB, TOUNIT); in sdhci_check_capareg()
157 val = FIELD_EX64(s->capareg, SDHC_CAPAB, TOCLKFREQ); in sdhci_check_capareg()
164 val = FIELD_EX64(s->capareg, SDHC_CAPAB, BASECLKFREQ); in sdhci_check_capareg()
171 val = FIELD_EX64(s->capareg, SDHC_CAPAB, MAXBLOCKLENGTH); in sdhci_check_capareg()
179 val = FIELD_EX64(s->capareg, SDHC_CAPAB, HIGHSPEED); in sdhci_check_capareg()
183 val = FIELD_EX64(s->capareg, SDHC_CAPAB, SDMA); in sdhci_check_capareg()
187 val = FIELD_EX64(s->capareg, SDHC_CAPAB, SUSPRESUME); in sdhci_check_capareg()
191 val = FIELD_EX64(s->capareg, SDHC_CAPAB, V33); in sdhci_check_capareg()
195 val = FIELD_EX64(s->capareg, SDHC_CAPAB, V30); in sdhci_check_capareg()
199 val = FIELD_EX64(s->capareg, SDHC_CAPAB, V18); in sdhci_check_capareg()
205 error_setg(errp, "Unsupported spec version: %u", s->sd_spec_version); in sdhci_check_capareg()
215 return (s->norintsts & s->norintsigen) || (s->errintsts & s->errintsigen) || in sdhci_slotint()
216 ((s->norintsts & SDHC_NIS_INSERT) && (s->wakcon & SDHC_WKUP_ON_INS)) || in sdhci_slotint()
217 ((s->norintsts & SDHC_NIS_REMOVE) && (s->wakcon & SDHC_WKUP_ON_RMV)); in sdhci_slotint()
225 qemu_set_irq(s->irq, pending); in sdhci_update_irq()
234 if (s->norintsts & SDHC_NIS_REMOVE) { in sdhci_raise_insertion_irq()
235 timer_mod(s->insert_timer, in sdhci_raise_insertion_irq()
238 s->prnsts = 0x1ff0000; in sdhci_raise_insertion_irq()
239 if (s->norintstsen & SDHC_NISEN_INSERT) { in sdhci_raise_insertion_irq()
240 s->norintsts |= SDHC_NIS_INSERT; in sdhci_raise_insertion_irq()
251 if ((s->norintsts & SDHC_NIS_REMOVE) && level) { in sdhci_set_inserted()
253 timer_mod(s->insert_timer, in sdhci_set_inserted()
257 s->prnsts = 0x1ff0000; in sdhci_set_inserted()
258 if (s->norintstsen & SDHC_NISEN_INSERT) { in sdhci_set_inserted()
259 s->norintsts |= SDHC_NIS_INSERT; in sdhci_set_inserted()
262 s->prnsts = 0x1fa0000; in sdhci_set_inserted()
263 s->pwrcon &= ~SDHC_POWER_ON; in sdhci_set_inserted()
264 s->clkcon &= ~SDHC_CLOCK_SDCLK_EN; in sdhci_set_inserted()
265 if (s->norintstsen & SDHC_NISEN_REMOVE) { in sdhci_set_inserted()
266 s->norintsts |= SDHC_NIS_REMOVE; in sdhci_set_inserted()
277 if (s->wp_inverted) { in sdhci_set_readonly()
282 s->prnsts &= ~SDHC_WRITE_PROTECT; in sdhci_set_readonly()
285 s->prnsts |= SDHC_WRITE_PROTECT; in sdhci_set_readonly()
293 timer_del(s->insert_timer); in sdhci_reset()
294 timer_del(s->transfer_timer); in sdhci_reset()
301 memset(&s->sdmasysad, 0, (uintptr_t)&s->capareg - (uintptr_t)&s->sdmasysad); in sdhci_reset()
304 sdhci_set_inserted(dev, sdbus_get_inserted(&s->sdbus)); in sdhci_reset()
305 sdhci_set_readonly(dev, sdbus_get_readonly(&s->sdbus)); in sdhci_reset()
307 s->data_count = 0; in sdhci_reset()
308 s->stopped_state = sdhc_not_stopped; in sdhci_reset()
309 s->pending_insert_state = false; in sdhci_reset()
310 if (s->vendor == SDHCI_VENDOR_FSL) { in sdhci_reset()
311 s->norintstsen = 0x013f; in sdhci_reset()
312 s->errintstsen = 0x117f; in sdhci_reset()
319 * QOM (ie power-on) reset. This is identical to reset in sdhci_poweron_reset()
327 if (s->pending_insert_quirk) { in sdhci_poweron_reset()
328 s->pending_insert_state = true; in sdhci_poweron_reset()
334 #define BLOCK_SIZE_MASK (4 * KiB - 1)
343 s->errintsts = 0; in sdhci_send_command()
344 s->acmd12errsts = 0; in sdhci_send_command()
345 request.cmd = s->cmdreg >> 8; in sdhci_send_command()
346 request.arg = s->argument; in sdhci_send_command()
349 rlen = sdbus_do_command(&s->sdbus, &request, response); in sdhci_send_command()
351 if (s->cmdreg & SDHC_CMD_RESPONSE) { in sdhci_send_command()
353 s->rspreg[0] = ldl_be_p(response); in sdhci_send_command()
354 s->rspreg[1] = s->rspreg[2] = s->rspreg[3] = 0; in sdhci_send_command()
355 trace_sdhci_response4(s->rspreg[0]); in sdhci_send_command()
357 s->rspreg[0] = ldl_be_p(&response[11]); in sdhci_send_command()
358 s->rspreg[1] = ldl_be_p(&response[7]); in sdhci_send_command()
359 s->rspreg[2] = ldl_be_p(&response[3]); in sdhci_send_command()
360 s->rspreg[3] = (response[0] << 16) | (response[1] << 8) | in sdhci_send_command()
362 trace_sdhci_response16(s->rspreg[3], s->rspreg[2], in sdhci_send_command()
363 s->rspreg[1], s->rspreg[0]); in sdhci_send_command()
367 if (s->errintstsen & SDHC_EISEN_CMDTIMEOUT) { in sdhci_send_command()
368 s->errintsts |= SDHC_EIS_CMDTIMEOUT; in sdhci_send_command()
369 s->norintsts |= SDHC_NIS_ERR; in sdhci_send_command()
373 if (!(s->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) && in sdhci_send_command()
374 (s->norintstsen & SDHC_NISEN_TRSCMP) && in sdhci_send_command()
375 (s->cmdreg & SDHC_CMD_RESPONSE) == SDHC_CMD_RSP_WITH_BUSY) { in sdhci_send_command()
376 s->norintsts |= SDHC_NIS_TRSCMP; in sdhci_send_command()
380 if (s->norintstsen & SDHC_NISEN_CMDCMP) { in sdhci_send_command()
381 s->norintsts |= SDHC_NIS_CMDCMP; in sdhci_send_command()
386 if (!timeout && (s->blksize & BLOCK_SIZE_MASK) && in sdhci_send_command()
387 (s->cmdreg & SDHC_CMD_DATA_PRESENT)) { in sdhci_send_command()
388 s->data_count = 0; in sdhci_send_command()
396 if ((s->trnmod & SDHC_TRNS_ACMD12) != 0) { in sdhci_end_transfer()
403 sdbus_do_command(&s->sdbus, &request, response); in sdhci_end_transfer()
405 s->rspreg[3] = ldl_be_p(response); in sdhci_end_transfer()
408 s->prnsts &= ~(SDHC_DOING_READ | SDHC_DOING_WRITE | in sdhci_end_transfer()
412 if (s->norintstsen & SDHC_NISEN_TRSCMP) { in sdhci_end_transfer()
413 s->norintsts |= SDHC_NIS_TRSCMP; in sdhci_end_transfer()
426 const uint16_t blk_size = s->blksize & BLOCK_SIZE_MASK; in sdhci_read_block_from_card()
428 if ((s->trnmod & SDHC_TRNS_MULTI) && in sdhci_read_block_from_card()
429 (s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0)) { in sdhci_read_block_from_card()
433 if (!FIELD_EX32(s->hostctl2, SDHC_HOSTCTL2, EXECUTE_TUNING)) { in sdhci_read_block_from_card()
435 sdbus_read_data(&s->sdbus, s->fifo_buffer, blk_size); in sdhci_read_block_from_card()
438 if (FIELD_EX32(s->hostctl2, SDHC_HOSTCTL2, EXECUTE_TUNING)) { in sdhci_read_block_from_card()
440 s->hostctl2 &= ~R_SDHC_HOSTCTL2_EXECUTE_TUNING_MASK; in sdhci_read_block_from_card()
441 s->hostctl2 |= R_SDHC_HOSTCTL2_SAMPLING_CLKSEL_MASK; in sdhci_read_block_from_card()
442 s->prnsts &= ~(SDHC_DAT_LINE_ACTIVE | SDHC_DOING_READ | in sdhci_read_block_from_card()
448 s->prnsts |= SDHC_DATA_AVAILABLE; in sdhci_read_block_from_card()
449 if (s->norintstsen & SDHC_NISEN_RBUFRDY) { in sdhci_read_block_from_card()
450 s->norintsts |= SDHC_NIS_RBUFRDY; in sdhci_read_block_from_card()
454 if ((s->trnmod & SDHC_TRNS_MULTI) == 0 || in sdhci_read_block_from_card()
455 ((s->trnmod & SDHC_TRNS_MULTI) && s->blkcnt == 1)) { in sdhci_read_block_from_card()
456 s->prnsts &= ~SDHC_DAT_LINE_ACTIVE; in sdhci_read_block_from_card()
461 * data - generate Block Event interrupt in sdhci_read_block_from_card()
463 if (s->stopped_state == sdhc_gap_read && (s->trnmod & SDHC_TRNS_MULTI) && in sdhci_read_block_from_card()
464 s->blkcnt != 1) { in sdhci_read_block_from_card()
465 s->prnsts &= ~SDHC_DAT_LINE_ACTIVE; in sdhci_read_block_from_card()
466 if (s->norintstsen & SDHC_EISEN_BLKGAP) { in sdhci_read_block_from_card()
467 s->norintsts |= SDHC_EIS_BLKGAP; in sdhci_read_block_from_card()
482 if ((s->prnsts & SDHC_DATA_AVAILABLE) == 0) { in sdhci_read_dataport()
488 assert(s->data_count < s->buf_maxsz); in sdhci_read_dataport()
489 value |= s->fifo_buffer[s->data_count] << i * 8; in sdhci_read_dataport()
490 s->data_count++; in sdhci_read_dataport()
492 if ((s->data_count) >= (s->blksize & BLOCK_SIZE_MASK)) { in sdhci_read_dataport()
493 trace_sdhci_read_dataport(s->data_count); in sdhci_read_dataport()
494 s->prnsts &= ~SDHC_DATA_AVAILABLE; /* no more data in a buffer */ in sdhci_read_dataport()
495 s->data_count = 0; /* next buff read must start at position [0] */ in sdhci_read_dataport()
497 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { in sdhci_read_dataport()
498 s->blkcnt--; in sdhci_read_dataport()
502 if ((s->trnmod & SDHC_TRNS_MULTI) == 0 || in sdhci_read_dataport()
503 ((s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0)) || in sdhci_read_dataport()
505 (s->stopped_state == sdhc_gap_read && in sdhci_read_dataport()
506 !(s->prnsts & SDHC_DAT_LINE_ACTIVE))) { in sdhci_read_dataport()
521 if (s->prnsts & SDHC_SPACE_AVAILABLE) { in sdhci_write_block_to_card()
522 if (s->norintstsen & SDHC_NISEN_WBUFRDY) { in sdhci_write_block_to_card()
523 s->norintsts |= SDHC_NIS_WBUFRDY; in sdhci_write_block_to_card()
529 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { in sdhci_write_block_to_card()
530 if (s->blkcnt == 0) { in sdhci_write_block_to_card()
533 s->blkcnt--; in sdhci_write_block_to_card()
537 sdbus_write_data(&s->sdbus, s->fifo_buffer, s->blksize & BLOCK_SIZE_MASK); in sdhci_write_block_to_card()
540 s->prnsts |= SDHC_SPACE_AVAILABLE; in sdhci_write_block_to_card()
543 if ((s->trnmod & SDHC_TRNS_MULTI) == 0 || in sdhci_write_block_to_card()
544 ((s->trnmod & SDHC_TRNS_MULTI) && in sdhci_write_block_to_card()
545 (s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0))) { in sdhci_write_block_to_card()
547 } else if (s->norintstsen & SDHC_NISEN_WBUFRDY) { in sdhci_write_block_to_card()
548 s->norintsts |= SDHC_NIS_WBUFRDY; in sdhci_write_block_to_card()
552 if (s->stopped_state == sdhc_gap_write && (s->trnmod & SDHC_TRNS_MULTI) && in sdhci_write_block_to_card()
553 s->blkcnt > 0) { in sdhci_write_block_to_card()
554 s->prnsts &= ~SDHC_DOING_WRITE; in sdhci_write_block_to_card()
555 if (s->norintstsen & SDHC_EISEN_BLKGAP) { in sdhci_write_block_to_card()
556 s->norintsts |= SDHC_EIS_BLKGAP; in sdhci_write_block_to_card()
573 if (!(s->prnsts & SDHC_SPACE_AVAILABLE)) { in sdhci_write_dataport()
579 assert(s->data_count < s->buf_maxsz); in sdhci_write_dataport()
580 s->fifo_buffer[s->data_count] = value & 0xFF; in sdhci_write_dataport()
581 s->data_count++; in sdhci_write_dataport()
583 if (s->data_count >= (s->blksize & BLOCK_SIZE_MASK)) { in sdhci_write_dataport()
584 trace_sdhci_write_dataport(s->data_count); in sdhci_write_dataport()
585 s->data_count = 0; in sdhci_write_dataport()
586 s->prnsts &= ~SDHC_SPACE_AVAILABLE; in sdhci_write_dataport()
587 if (s->prnsts & SDHC_DOING_WRITE) { in sdhci_write_dataport()
598 /* Multi block SDMA transfer */
603 const uint16_t block_size = s->blksize & BLOCK_SIZE_MASK; in sdhci_sdma_transfer_multi_blocks()
604 uint32_t boundary_chk = 1 << (((s->blksize & ~BLOCK_SIZE_MASK) >> 12) + 12); in sdhci_sdma_transfer_multi_blocks()
605 uint32_t boundary_count = boundary_chk - (s->sdmasysad % boundary_chk); in sdhci_sdma_transfer_multi_blocks()
607 if (!(s->trnmod & SDHC_TRNS_BLK_CNT_EN) || !s->blkcnt) { in sdhci_sdma_transfer_multi_blocks()
613 * XXX: Some sd/mmc drivers (for example, u-boot-slp) do not account for in sdhci_sdma_transfer_multi_blocks()
617 if ((s->sdmasysad % boundary_chk) == 0) { in sdhci_sdma_transfer_multi_blocks()
621 s->prnsts |= SDHC_DATA_INHIBIT | SDHC_DAT_LINE_ACTIVE; in sdhci_sdma_transfer_multi_blocks()
622 if (s->trnmod & SDHC_TRNS_READ) { in sdhci_sdma_transfer_multi_blocks()
623 s->prnsts |= SDHC_DOING_READ; in sdhci_sdma_transfer_multi_blocks()
624 while (s->blkcnt) { in sdhci_sdma_transfer_multi_blocks()
625 if (s->data_count == 0) { in sdhci_sdma_transfer_multi_blocks()
626 sdbus_read_data(&s->sdbus, s->fifo_buffer, block_size); in sdhci_sdma_transfer_multi_blocks()
628 begin = s->data_count; in sdhci_sdma_transfer_multi_blocks()
630 s->data_count = boundary_count + begin; in sdhci_sdma_transfer_multi_blocks()
633 s->data_count = block_size; in sdhci_sdma_transfer_multi_blocks()
634 boundary_count -= block_size - begin; in sdhci_sdma_transfer_multi_blocks()
635 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { in sdhci_sdma_transfer_multi_blocks()
636 s->blkcnt--; in sdhci_sdma_transfer_multi_blocks()
639 dma_memory_write(s->dma_as, s->sdmasysad, &s->fifo_buffer[begin], in sdhci_sdma_transfer_multi_blocks()
640 s->data_count - begin, MEMTXATTRS_UNSPECIFIED); in sdhci_sdma_transfer_multi_blocks()
641 s->sdmasysad += s->data_count - begin; in sdhci_sdma_transfer_multi_blocks()
642 if (s->data_count == block_size) { in sdhci_sdma_transfer_multi_blocks()
643 s->data_count = 0; in sdhci_sdma_transfer_multi_blocks()
650 s->prnsts |= SDHC_DOING_WRITE; in sdhci_sdma_transfer_multi_blocks()
651 while (s->blkcnt) { in sdhci_sdma_transfer_multi_blocks()
652 begin = s->data_count; in sdhci_sdma_transfer_multi_blocks()
654 s->data_count = boundary_count + begin; in sdhci_sdma_transfer_multi_blocks()
657 s->data_count = block_size; in sdhci_sdma_transfer_multi_blocks()
658 boundary_count -= block_size - begin; in sdhci_sdma_transfer_multi_blocks()
660 dma_memory_read(s->dma_as, s->sdmasysad, &s->fifo_buffer[begin], in sdhci_sdma_transfer_multi_blocks()
661 s->data_count - begin, MEMTXATTRS_UNSPECIFIED); in sdhci_sdma_transfer_multi_blocks()
662 s->sdmasysad += s->data_count - begin; in sdhci_sdma_transfer_multi_blocks()
663 if (s->data_count == block_size) { in sdhci_sdma_transfer_multi_blocks()
664 sdbus_write_data(&s->sdbus, s->fifo_buffer, block_size); in sdhci_sdma_transfer_multi_blocks()
665 s->data_count = 0; in sdhci_sdma_transfer_multi_blocks()
666 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { in sdhci_sdma_transfer_multi_blocks()
667 s->blkcnt--; in sdhci_sdma_transfer_multi_blocks()
676 if (s->norintstsen & SDHC_NISEN_DMA) { in sdhci_sdma_transfer_multi_blocks()
677 s->norintsts |= SDHC_NIS_DMA; in sdhci_sdma_transfer_multi_blocks()
680 if (s->blkcnt == 0) { in sdhci_sdma_transfer_multi_blocks()
690 uint32_t datacnt = s->blksize & BLOCK_SIZE_MASK; in sdhci_sdma_transfer_single_block()
692 if (s->trnmod & SDHC_TRNS_READ) { in sdhci_sdma_transfer_single_block()
693 sdbus_read_data(&s->sdbus, s->fifo_buffer, datacnt); in sdhci_sdma_transfer_single_block()
694 dma_memory_write(s->dma_as, s->sdmasysad, s->fifo_buffer, datacnt, in sdhci_sdma_transfer_single_block()
697 dma_memory_read(s->dma_as, s->sdmasysad, s->fifo_buffer, datacnt, in sdhci_sdma_transfer_single_block()
699 sdbus_write_data(&s->sdbus, s->fifo_buffer, datacnt); in sdhci_sdma_transfer_single_block()
701 s->blkcnt--; in sdhci_sdma_transfer_single_block()
703 if (s->norintstsen & SDHC_NISEN_DMA) { in sdhci_sdma_transfer_single_block()
704 s->norintsts |= SDHC_NIS_DMA; in sdhci_sdma_transfer_single_block()
712 if ((s->blkcnt == 1) || !(s->trnmod & SDHC_TRNS_MULTI)) { in sdhci_sdma_transfer()
722 uint8_t attr; member
730 hwaddr entry_addr = (hwaddr)s->admasysaddr; in get_adma_description()
731 switch (SDHC_DMA_TYPE(s->hostctl1)) { in get_adma_description()
733 dma_memory_read(s->dma_as, entry_addr, &adma2, sizeof(adma2), in get_adma_description()
740 dscr->addr = (hwaddr)extract64(adma2, 32, 32) & ~0x3ull; in get_adma_description()
741 dscr->length = (uint16_t)extract64(adma2, 16, 16); in get_adma_description()
742 dscr->attr = (uint8_t)extract64(adma2, 0, 7); in get_adma_description()
743 dscr->incr = 8; in get_adma_description()
746 dma_memory_read(s->dma_as, entry_addr, &adma1, sizeof(adma1), in get_adma_description()
749 dscr->addr = (hwaddr)(adma1 & 0xFFFFF000); in get_adma_description()
750 dscr->attr = (uint8_t)extract32(adma1, 0, 7); in get_adma_description()
751 dscr->incr = 4; in get_adma_description()
752 if ((dscr->attr & SDHC_ADMA_ATTR_ACT_MASK) == SDHC_ADMA_ATTR_SET_LEN) { in get_adma_description()
753 dscr->length = (uint16_t)extract32(adma1, 12, 16); in get_adma_description()
755 dscr->length = 4 * KiB; in get_adma_description()
759 dma_memory_read(s->dma_as, entry_addr, &dscr->attr, 1, in get_adma_description()
761 dma_memory_read(s->dma_as, entry_addr + 2, &dscr->length, 2, in get_adma_description()
763 dscr->length = le16_to_cpu(dscr->length); in get_adma_description()
764 dma_memory_read(s->dma_as, entry_addr + 4, &dscr->addr, 8, in get_adma_description()
766 dscr->addr = le64_to_cpu(dscr->addr); in get_adma_description()
767 dscr->attr &= (uint8_t) ~0xC0; in get_adma_description()
768 dscr->incr = 12; in get_adma_description()
778 const uint16_t block_size = s->blksize & BLOCK_SIZE_MASK; in sdhci_do_adma()
784 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN && !s->blkcnt) { in sdhci_do_adma()
791 s->admaerr &= ~SDHC_ADMAERR_LENGTH_MISMATCH; in sdhci_do_adma()
794 trace_sdhci_adma_loop(dscr.addr, dscr.length, dscr.attr); in sdhci_do_adma()
796 if ((dscr.attr & SDHC_ADMA_ATTR_VALID) == 0) { in sdhci_do_adma()
798 s->admaerr &= ~SDHC_ADMAERR_STATE_MASK; in sdhci_do_adma()
799 s->admaerr |= SDHC_ADMAERR_STATE_ST_FDS; in sdhci_do_adma()
802 if (s->errintstsen & SDHC_EISEN_ADMAERR) { in sdhci_do_adma()
803 s->errintsts |= SDHC_EIS_ADMAERR; in sdhci_do_adma()
804 s->norintsts |= SDHC_NIS_ERR; in sdhci_do_adma()
813 switch (dscr.attr & SDHC_ADMA_ATTR_ACT_MASK) { in sdhci_do_adma()
815 s->prnsts |= SDHC_DATA_INHIBIT | SDHC_DAT_LINE_ACTIVE; in sdhci_do_adma()
816 if (s->trnmod & SDHC_TRNS_READ) { in sdhci_do_adma()
817 s->prnsts |= SDHC_DOING_READ; in sdhci_do_adma()
819 if (s->data_count == 0) { in sdhci_do_adma()
820 sdbus_read_data(&s->sdbus, s->fifo_buffer, block_size); in sdhci_do_adma()
822 begin = s->data_count; in sdhci_do_adma()
824 s->data_count = length + begin; in sdhci_do_adma()
827 s->data_count = block_size; in sdhci_do_adma()
828 length -= block_size - begin; in sdhci_do_adma()
830 res = dma_memory_write(s->dma_as, dscr.addr, in sdhci_do_adma()
831 &s->fifo_buffer[begin], in sdhci_do_adma()
832 s->data_count - begin, in sdhci_do_adma()
837 dscr.addr += s->data_count - begin; in sdhci_do_adma()
838 if (s->data_count == block_size) { in sdhci_do_adma()
839 s->data_count = 0; in sdhci_do_adma()
840 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { in sdhci_do_adma()
841 s->blkcnt--; in sdhci_do_adma()
842 if (s->blkcnt == 0) { in sdhci_do_adma()
849 s->prnsts |= SDHC_DOING_WRITE; in sdhci_do_adma()
851 begin = s->data_count; in sdhci_do_adma()
853 s->data_count = length + begin; in sdhci_do_adma()
856 s->data_count = block_size; in sdhci_do_adma()
857 length -= block_size - begin; in sdhci_do_adma()
859 res = dma_memory_read(s->dma_as, dscr.addr, in sdhci_do_adma()
860 &s->fifo_buffer[begin], in sdhci_do_adma()
861 s->data_count - begin, in sdhci_do_adma()
866 dscr.addr += s->data_count - begin; in sdhci_do_adma()
867 if (s->data_count == block_size) { in sdhci_do_adma()
868 sdbus_write_data(&s->sdbus, s->fifo_buffer, block_size); in sdhci_do_adma()
869 s->data_count = 0; in sdhci_do_adma()
870 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { in sdhci_do_adma()
871 s->blkcnt--; in sdhci_do_adma()
872 if (s->blkcnt == 0) { in sdhci_do_adma()
880 s->data_count = 0; in sdhci_do_adma()
881 if (s->errintstsen & SDHC_EISEN_ADMAERR) { in sdhci_do_adma()
883 s->errintsts |= SDHC_EIS_ADMAERR; in sdhci_do_adma()
884 s->norintsts |= SDHC_NIS_ERR; in sdhci_do_adma()
888 s->admasysaddr += dscr.incr; in sdhci_do_adma()
892 s->admasysaddr = dscr.addr; in sdhci_do_adma()
893 trace_sdhci_adma("link", s->admasysaddr); in sdhci_do_adma()
896 s->admasysaddr += dscr.incr; in sdhci_do_adma()
900 if (dscr.attr & SDHC_ADMA_ATTR_INT) { in sdhci_do_adma()
901 trace_sdhci_adma("interrupt", s->admasysaddr); in sdhci_do_adma()
902 if (s->norintstsen & SDHC_NISEN_DMA) { in sdhci_do_adma()
903 s->norintsts |= SDHC_NIS_DMA; in sdhci_do_adma()
906 if (sdhci_update_irq(s) && !(dscr.attr & SDHC_ADMA_ATTR_END)) { in sdhci_do_adma()
913 if (((s->trnmod & SDHC_TRNS_BLK_CNT_EN) && in sdhci_do_adma()
914 (s->blkcnt == 0)) || (dscr.attr & SDHC_ADMA_ATTR_END)) { in sdhci_do_adma()
916 if (length || ((dscr.attr & SDHC_ADMA_ATTR_END) && in sdhci_do_adma()
917 (s->trnmod & SDHC_TRNS_BLK_CNT_EN) && in sdhci_do_adma()
918 s->blkcnt != 0)) { in sdhci_do_adma()
920 s->admaerr |= SDHC_ADMAERR_LENGTH_MISMATCH | in sdhci_do_adma()
922 if (s->errintstsen & SDHC_EISEN_ADMAERR) { in sdhci_do_adma()
924 s->errintsts |= SDHC_EIS_ADMAERR; in sdhci_do_adma()
925 s->norintsts |= SDHC_NIS_ERR; in sdhci_do_adma()
936 /* we have unfinished business - reschedule to continue ADMA */ in sdhci_do_adma()
937 timer_mod(s->transfer_timer, in sdhci_do_adma()
947 if (s->trnmod & SDHC_TRNS_DMA) { in sdhci_data_transfer()
948 switch (SDHC_DMA_TYPE(s->hostctl1)) { in sdhci_data_transfer()
953 if (!(s->capareg & R_SDHC_CAPAB_ADMA1_MASK)) { in sdhci_data_transfer()
961 if (!(s->capareg & R_SDHC_CAPAB_ADMA2_MASK)) { in sdhci_data_transfer()
969 if (!(s->capareg & R_SDHC_CAPAB_ADMA2_MASK) || in sdhci_data_transfer()
970 !(s->capareg & R_SDHC_CAPAB_BUS64BIT_MASK)) { in sdhci_data_transfer()
982 if ((s->trnmod & SDHC_TRNS_READ) && sdbus_data_ready(&s->sdbus)) { in sdhci_data_transfer()
983 s->prnsts |= SDHC_DOING_READ | SDHC_DATA_INHIBIT | in sdhci_data_transfer()
987 s->prnsts |= SDHC_DOING_WRITE | SDHC_DAT_LINE_ACTIVE | in sdhci_data_transfer()
996 if (!SDHC_CLOCK_IS_ON(s->clkcon) || in sdhci_can_issue_command()
997 (((s->prnsts & SDHC_DATA_INHIBIT) || s->stopped_state) && in sdhci_can_issue_command()
998 ((s->cmdreg & SDHC_CMD_DATA_PRESENT) || in sdhci_can_issue_command()
999 ((s->cmdreg & SDHC_CMD_RESPONSE) == SDHC_CMD_RSP_WITH_BUSY && in sdhci_can_issue_command()
1000 !(SDHC_COMMAND_TYPE(s->cmdreg) == SDHC_CMD_ABORT))))) { in sdhci_can_issue_command()
1014 if ((s->data_count & 0x3) != byte_num) { in sdhci_buff_access_is_sequential()
1016 "SDHCI: Non-sequential access to Buffer Data Port" in sdhci_buff_access_is_sequential()
1025 timer_del(s->transfer_timer); in sdhci_resume_pending_transfer()
1034 if (timer_pending(s->transfer_timer)) { in sdhci_read()
1040 ret = s->sdmasysad; in sdhci_read()
1043 ret = s->blksize | (s->blkcnt << 16); in sdhci_read()
1046 ret = s->argument; in sdhci_read()
1049 ret = s->trnmod | (s->cmdreg << 16); in sdhci_read()
1052 ret = s->rspreg[((offset & ~0x3) - SDHC_RSPREG0) >> 2]; in sdhci_read()
1055 if (sdhci_buff_access_is_sequential(s, offset - SDHC_BDATA)) { in sdhci_read()
1057 trace_sdhci_access("rd", size << 3, offset, "->", ret, ret); in sdhci_read()
1062 ret = s->prnsts; in sdhci_read()
1064 sdbus_get_dat_lines(&s->sdbus)); in sdhci_read()
1066 sdbus_get_cmd_line(&s->sdbus)); in sdhci_read()
1069 ret = s->hostctl1 | (s->pwrcon << 8) | (s->blkgap << 16) | in sdhci_read()
1070 (s->wakcon << 24); in sdhci_read()
1073 ret = s->clkcon | (s->timeoutcon << 16); in sdhci_read()
1076 ret = s->norintsts | (s->errintsts << 16); in sdhci_read()
1079 ret = s->norintstsen | (s->errintstsen << 16); in sdhci_read()
1082 ret = s->norintsigen | (s->errintsigen << 16); in sdhci_read()
1085 ret = s->acmd12errsts | (s->hostctl2 << 16); in sdhci_read()
1088 ret = (uint32_t)s->capareg; in sdhci_read()
1091 ret = (uint32_t)(s->capareg >> 32); in sdhci_read()
1094 ret = (uint32_t)s->maxcurr; in sdhci_read()
1097 ret = (uint32_t)(s->maxcurr >> 32); in sdhci_read()
1100 ret = s->admaerr; in sdhci_read()
1103 ret = (uint32_t)s->admasysaddr; in sdhci_read()
1106 ret = (uint32_t)(s->admasysaddr >> 32); in sdhci_read()
1109 ret = (s->version << 16) | sdhci_slotint(s); in sdhci_read()
1118 ret &= (1ULL << (size * 8)) - 1; in sdhci_read()
1119 trace_sdhci_access("rd", size << 3, offset, "->", ret, ret); in sdhci_read()
1125 if ((value & SDHC_STOP_AT_GAP_REQ) && (s->blkgap & SDHC_STOP_AT_GAP_REQ)) { in sdhci_blkgap_write()
1128 s->blkgap = value & SDHC_STOP_AT_GAP_REQ; in sdhci_blkgap_write()
1130 if ((value & SDHC_CONTINUE_REQ) && s->stopped_state && in sdhci_blkgap_write()
1131 (s->blkgap & SDHC_STOP_AT_GAP_REQ) == 0) { in sdhci_blkgap_write()
1132 if (s->stopped_state == sdhc_gap_read) { in sdhci_blkgap_write()
1133 s->prnsts |= SDHC_DAT_LINE_ACTIVE | SDHC_DOING_READ; in sdhci_blkgap_write()
1136 s->prnsts |= SDHC_DAT_LINE_ACTIVE | SDHC_DOING_WRITE; in sdhci_blkgap_write()
1139 s->stopped_state = sdhc_not_stopped; in sdhci_blkgap_write()
1140 } else if (!s->stopped_state && (value & SDHC_STOP_AT_GAP_REQ)) { in sdhci_blkgap_write()
1141 if (s->prnsts & SDHC_DOING_READ) { in sdhci_blkgap_write()
1142 s->stopped_state = sdhc_gap_read; in sdhci_blkgap_write()
1143 } else if (s->prnsts & SDHC_DOING_WRITE) { in sdhci_blkgap_write()
1144 s->stopped_state = sdhc_gap_write; in sdhci_blkgap_write()
1156 s->prnsts &= ~SDHC_CMD_INHIBIT; in sdhci_reset_write()
1157 s->norintsts &= ~SDHC_NIS_CMDCMP; in sdhci_reset_write()
1160 s->data_count = 0; in sdhci_reset_write()
1161 s->prnsts &= ~(SDHC_SPACE_AVAILABLE | SDHC_DATA_AVAILABLE | in sdhci_reset_write()
1164 s->blkgap &= ~(SDHC_STOP_AT_GAP_REQ | SDHC_CONTINUE_REQ); in sdhci_reset_write()
1165 s->stopped_state = sdhc_not_stopped; in sdhci_reset_write()
1166 s->norintsts &= ~(SDHC_NIS_WBUFRDY | SDHC_NIS_RBUFRDY | in sdhci_reset_write()
1177 uint32_t mask = ~(((1ULL << (size * 8)) - 1) << shift); in sdhci_write()
1181 if (timer_pending(s->transfer_timer)) { in sdhci_write()
1187 if (!TRANSFERRING_DATA(s->prnsts)) { in sdhci_write()
1188 s->sdmasysad = (s->sdmasysad & mask) | value; in sdhci_write()
1189 MASKED_WRITE(s->sdmasysad, mask, value); in sdhci_write()
1191 if (!(mask & 0xFF000000) && s->blkcnt && in sdhci_write()
1192 (s->blksize & BLOCK_SIZE_MASK) && in sdhci_write()
1193 SDHC_DMA_TYPE(s->hostctl1) == SDHC_CTRL_SDMA) { in sdhci_write()
1199 if (!TRANSFERRING_DATA(s->prnsts)) { in sdhci_write()
1200 uint16_t blksize = s->blksize; in sdhci_write()
1206 MASKED_WRITE(s->blksize, mask, extract32(value, 0, 15)); in sdhci_write()
1207 MASKED_WRITE(s->blkcnt, mask >> 16, value >> 16); in sdhci_write()
1210 if (extract32(s->blksize, 0, 12) > s->buf_maxsz) { in sdhci_write()
1212 "the maximum buffer 0x%x\n", __func__, s->blksize, in sdhci_write()
1213 s->buf_maxsz); in sdhci_write()
1215 s->blksize = deposit32(s->blksize, 0, 12, s->buf_maxsz); in sdhci_write()
1220 * the previous one, reset the data pointer of s->fifo_buffer[] in sdhci_write()
1221 * so that s->fifo_buffer[] can be filled in using the new block in sdhci_write()
1224 if (blksize != s->blksize) { in sdhci_write()
1225 s->data_count = 0; in sdhci_write()
1231 MASKED_WRITE(s->argument, mask, value); in sdhci_write()
1238 if (!(s->capareg & R_SDHC_CAPAB_SDMA_MASK)) { in sdhci_write()
1243 if (s->prnsts & SDHC_DATA_INHIBIT) { in sdhci_write()
1247 MASKED_WRITE(s->trnmod, mask, value & SDHC_TRNMOD_MASK); in sdhci_write()
1248 MASKED_WRITE(s->cmdreg, mask >> 16, value >> 16); in sdhci_write()
1258 if (sdhci_buff_access_is_sequential(s, offset - SDHC_BDATA)) { in sdhci_write()
1266 MASKED_WRITE(s->hostctl1, mask, value); in sdhci_write()
1267 MASKED_WRITE(s->pwrcon, mask >> 8, value >> 8); in sdhci_write()
1268 MASKED_WRITE(s->wakcon, mask >> 24, value >> 24); in sdhci_write()
1269 if (!(s->prnsts & SDHC_CARD_PRESENT) || ((s->pwrcon >> 1) & 0x7) < 5 || in sdhci_write()
1270 !(s->capareg & (1 << (31 - ((s->pwrcon >> 1) & 0x7))))) { in sdhci_write()
1271 s->pwrcon &= ~SDHC_POWER_ON; in sdhci_write()
1278 MASKED_WRITE(s->clkcon, mask, value); in sdhci_write()
1279 MASKED_WRITE(s->timeoutcon, mask >> 16, value >> 16); in sdhci_write()
1280 if (s->clkcon & SDHC_CLOCK_INT_EN) { in sdhci_write()
1281 s->clkcon |= SDHC_CLOCK_INT_STABLE; in sdhci_write()
1283 s->clkcon &= ~SDHC_CLOCK_INT_STABLE; in sdhci_write()
1287 if (s->norintstsen & SDHC_NISEN_CARDINT) { in sdhci_write()
1290 s->norintsts &= mask | ~value; in sdhci_write()
1291 s->errintsts &= (mask >> 16) | ~(value >> 16); in sdhci_write()
1292 if (s->errintsts) { in sdhci_write()
1293 s->norintsts |= SDHC_NIS_ERR; in sdhci_write()
1295 s->norintsts &= ~SDHC_NIS_ERR; in sdhci_write()
1300 MASKED_WRITE(s->norintstsen, mask, value); in sdhci_write()
1301 MASKED_WRITE(s->errintstsen, mask >> 16, value >> 16); in sdhci_write()
1302 s->norintsts &= s->norintstsen; in sdhci_write()
1303 s->errintsts &= s->errintstsen; in sdhci_write()
1304 if (s->errintsts) { in sdhci_write()
1305 s->norintsts |= SDHC_NIS_ERR; in sdhci_write()
1307 s->norintsts &= ~SDHC_NIS_ERR; in sdhci_write()
1313 if ((s->norintstsen & SDHC_NISEN_INSERT) && s->pending_insert_state) { in sdhci_write()
1314 assert(s->pending_insert_quirk); in sdhci_write()
1315 s->norintsts |= SDHC_NIS_INSERT; in sdhci_write()
1316 s->pending_insert_state = false; in sdhci_write()
1321 MASKED_WRITE(s->norintsigen, mask, value); in sdhci_write()
1322 MASKED_WRITE(s->errintsigen, mask >> 16, value >> 16); in sdhci_write()
1326 MASKED_WRITE(s->admaerr, mask, value); in sdhci_write()
1329 s->admasysaddr = (s->admasysaddr & (0xFFFFFFFF00000000ULL | in sdhci_write()
1333 s->admasysaddr = (s->admasysaddr & (0x00000000FFFFFFFFULL | in sdhci_write()
1337 s->acmd12errsts |= value; in sdhci_write()
1338 s->errintsts |= (value >> 16) & s->errintstsen; in sdhci_write()
1339 if (s->acmd12errsts) { in sdhci_write()
1340 s->errintsts |= SDHC_EIS_CMD12ERR; in sdhci_write()
1342 if (s->errintsts) { in sdhci_write()
1343 s->norintsts |= SDHC_NIS_ERR; in sdhci_write()
1348 MASKED_WRITE(s->acmd12errsts, mask, value & UINT16_MAX); in sdhci_write()
1349 if (s->uhs_mode >= UHS_I) { in sdhci_write()
1350 MASKED_WRITE(s->hostctl2, mask >> 16, value >> 16); in sdhci_write()
1352 if (FIELD_EX32(s->hostctl2, SDHC_HOSTCTL2, V18_ENA)) { in sdhci_write()
1353 sdbus_set_voltage(&s->sdbus, SD_VOLTAGE_1_8V); in sdhci_write()
1355 sdbus_set_voltage(&s->sdbus, SD_VOLTAGE_3_3V); in sdhci_write()
1365 " <- 0x%08x read-only\n", size, offset, value >> shift); in sdhci_write()
1369 qemu_log_mask(LOG_UNIMP, "SDHC wr_%ub @0x%02" HWADDR_PRIx " <- 0x%08x " in sdhci_write()
1373 trace_sdhci_access("wr", size << 3, offset, "<-", in sdhci_write()
1407 switch (s->sd_spec_version) { in sdhci_init_readonly_registers()
1414 s->version = (SDHC_HCVER_VENDOR << 8) | (s->sd_spec_version - 1); in sdhci_init_readonly_registers()
1422 /* --- qdev common --- */
1426 qbus_init(&s->sdbus, sizeof(s->sdbus), TYPE_SDHCI_BUS, DEVICE(s), "sd-bus"); in sdhci_initfn()
1428 s->insert_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, in sdhci_initfn()
1430 s->transfer_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, in sdhci_initfn()
1433 s->io_ops = &sdhci_mmio_le_ops; in sdhci_initfn()
1438 timer_free(s->insert_timer); in sdhci_uninitfn()
1439 timer_free(s->transfer_timer); in sdhci_uninitfn()
1441 g_free(s->fifo_buffer); in sdhci_uninitfn()
1442 s->fifo_buffer = NULL; in sdhci_uninitfn()
1449 switch (s->endianness) { in sdhci_common_realize()
1451 /* s->io_ops is little endian by default */ in sdhci_common_realize()
1454 if (s->io_ops != &sdhci_mmio_le_ops) { in sdhci_common_realize()
1458 s->io_ops = &sdhci_mmio_be_ops; in sdhci_common_realize()
1470 s->buf_maxsz = sdhci_get_fifolen(s); in sdhci_common_realize()
1471 s->fifo_buffer = g_malloc0(s->buf_maxsz); in sdhci_common_realize()
1473 memory_region_init_io(&s->iomem, OBJECT(s), s->io_ops, s, "sdhci", in sdhci_common_realize()
1481 * - SysBus: via DeviceClass->unrealize(), in sdhci_common_unrealize()
1482 * - PCI: via PCIDeviceClass->exit(). in sdhci_common_unrealize()
1483 * However to avoid double-free and/or use-after-free we still nullify in sdhci_common_unrealize()
1486 g_free(s->fifo_buffer); in sdhci_common_unrealize()
1487 s->fifo_buffer = NULL; in sdhci_common_unrealize()
1494 return s->pending_insert_state; in sdhci_pending_insert_vmstate_needed()
1498 .name = "sdhci/pending-insert",
1553 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); in sdhci_common_class_init()
1554 dc->vmsd = &sdhci_vmstate; in sdhci_common_class_init()
1558 /* --- qdev SysBus --- */
1562 DEFINE_PROP_BOOL("pending-insert-quirk", SDHCIState, pending_insert_quirk,
1566 DEFINE_PROP_BOOL("wp-inverted", SDHCIState,
1581 if (s->dma_mr) { in sdhci_sysbus_finalize()
1582 object_unparent(OBJECT(s->dma_mr)); in sdhci_sysbus_finalize()
1599 if (s->dma_mr) { in sdhci_sysbus_realize()
1600 s->dma_as = &s->sysbus_dma_as; in sdhci_sysbus_realize()
1601 address_space_init(s->dma_as, s->dma_mr, "sdhci-dma"); in sdhci_sysbus_realize()
1604 s->dma_as = &address_space_memory; in sdhci_sysbus_realize()
1607 sysbus_init_irq(sbd, &s->irq); in sdhci_sysbus_realize()
1609 sysbus_init_mmio(sbd, &s->iomem); in sdhci_sysbus_realize()
1618 if (s->dma_mr) { in sdhci_sysbus_unrealize()
1619 address_space_destroy(s->dma_as); in sdhci_sysbus_unrealize()
1628 dc->realize = sdhci_sysbus_realize; in sdhci_sysbus_class_init()
1629 dc->unrealize = sdhci_sysbus_unrealize; in sdhci_sysbus_class_init()
1634 /* --- qdev bus master --- */
1640 sbc->set_inserted = sdhci_set_inserted; in sdhci_bus_class_init()
1641 sbc->set_readonly = sdhci_set_readonly; in sdhci_bus_class_init()
1644 /* --- qdev i.MX eSDHC --- */
1681 hostctl1 = SDHC_DMA_TYPE(s->hostctl1) << (8 - 3); in usdhc_read()
1683 if (s->hostctl1 & SDHC_CTRL_8BITBUS) { in usdhc_read()
1687 if (s->hostctl1 & SDHC_CTRL_4BITBUS) { in usdhc_read()
1692 ret |= (uint32_t)s->blkgap << 16; in usdhc_read()
1693 ret |= (uint32_t)s->wakcon << 24; in usdhc_read()
1700 if (s->clkcon & SDHC_CLOCK_INT_STABLE) { in usdhc_read()
1706 ret = s->vendor_spec; in usdhc_read()
1737 s->vendor_spec = value; in usdhc_write()
1739 s->prnsts &= ~SDHC_IMX_CLOCK_GATE_OFF; in usdhc_write()
1741 s->prnsts |= SDHC_IMX_CLOCK_GATE_OFF; in usdhc_write()
1750 * |-----------+--------+--------+-----------+----------+---------| in usdhc_write()
1755 * |-----------+--------+--------+-----------+----------+---------| in usdhc_write()
1760 * |----------+------| in usdhc_write()
1764 * |----------+------| in usdhc_write()
1771 * |--------+--------+----------+------+--------+----------+---------| in usdhc_write()
1776 * |--------+--------+----------+------+--------+----------+---------| in usdhc_write()
1780 * |----------------------------------| in usdhc_write()
1786 * |----------------------------------| in usdhc_write()
1789 * both IP specs we only need to reconcile least 16-bit of the in usdhc_write()
1814 hostctl1 |= SDHC_DMA_TYPE(value >> (8 - 3)); in usdhc_write()
1817 * Now place the corrected value into low 16-bit of the value in usdhc_write()
1821 * be found in drivers/mmc/host/sdhci-esdhc-imx.c in Linux in usdhc_write()
1826 value |= (uint16_t)s->pwrcon << 8; in usdhc_write()
1846 s->trnmod = value & UINT16_MAX; in usdhc_write()
1851 * Register" will be translated into a 4-byte write to in usdhc_write()
1852 * "Transfer Mode register" where lower 16-bit of value would in usdhc_write()
1854 * cached value from s->trnmod and let the SDHCI in usdhc_write()
1857 sdhci_write(opaque, offset, val | s->trnmod, size); in usdhc_write()
1892 s->io_ops = &usdhc_mmio_ops; in imx_usdhc_init()
1893 s->quirks = SDHCI_QUIRK_NO_BUSY_IRQ; in imx_usdhc_init()
1896 /* --- qdev Samsung s3c --- */
1951 s->io_ops = &sdhci_s3c_mmio_ops; in sdhci_s3c_init()