87 #define PL181_CMD_INDEX     0x3f
94 #define PL181_DATA_ENABLE             (1 << 0)
99 #define PL181_STATUS_CMDCRCFAIL       (1 << 0)
133 { 0x81, 0x11, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
138     for (i = 0; i < 2; i++) {  in pl181_update()
139         qemu_set_irq(s->irq[i], (s->status & s->mask[i]) != 0);  in pl181_update()
161     if (s->fifo_len == 0) {  in pl181_fifo_pop()
163         return 0;  in pl181_fifo_pop()
182     if (rlen < 0)  in pl181_do_command()
185         if (rlen == 0 || (rlen == 4 && (s->cmd & PL181_CMD_LONGRESP)))  in pl181_do_command()
189         s->response[0] = ldl_be_p(&response[0]);  in pl181_do_command()
191             s->response[1] = s->response[2] = s->response[3] = 0;  in pl181_do_command()
217     uint32_t value = 0;  in pl181_fifo_run()
221     is_read = (s->datactrl & PL181_DATA_DIRECTION) != 0;  in pl181_fifo_run()
222     if (s->datacnt != 0 && (!is_read || sdbus_data_ready(&s->sdbus))  in pl181_fifo_run()
225             n = 0;  in pl181_fifo_run()
232                     n = 0;  in pl181_fifo_run()
233                     value = 0;  in pl181_fifo_run()
236             if (n != 0) {  in pl181_fifo_run()
240             n = 0;  in pl181_fifo_run()
241             while (s->datacnt > 0 && (s->fifo_len > 0 || n > 0)) {  in pl181_fifo_run()
242                 if (n == 0) {  in pl181_fifo_run()
248                 sdbus_write_byte(&s->sdbus, value & 0xff);  in pl181_fifo_run()
254     if (s->datacnt == 0) {  in pl181_fifo_run()
260     if (s->datacnt == 0 && s->fifo_len == 0) {  in pl181_fifo_run()
266         if (s->fifo_len == 0) {  in pl181_fifo_run()
298     if (offset >= 0xfe0 && offset < 0x1000) {  in pl181_read()
299         return pl181_id[(offset - 0xfe0) >> 2];  in pl181_read()
302     case 0x00: /* Power */  in pl181_read()
304     case 0x04: /* Clock */  in pl181_read()
306     case 0x08: /* Argument */  in pl181_read()
308     case 0x0c: /* Command */  in pl181_read()
310     case 0x10: /* RespCmd */  in pl181_read()
312     case 0x14: /* Response0 */  in pl181_read()
313         return s->response[0];  in pl181_read()
314     case 0x18: /* Response1 */  in pl181_read()
316     case 0x1c: /* Response2 */  in pl181_read()
318     case 0x20: /* Response3 */  in pl181_read()
320     case 0x24: /* DataTimer */  in pl181_read()
322     case 0x28: /* DataLength */  in pl181_read()
324     case 0x2c: /* DataCtrl */  in pl181_read()
326     case 0x30: /* DataCnt */  in pl181_read()
328     case 0x34: /* Status */  in pl181_read()
331             s->linux_hack = 0;  in pl181_read()
336     case 0x3c: /* Mask0 */  in pl181_read()
337         return s->mask[0];  in pl181_read()
338     case 0x40: /* Mask1 */  in pl181_read()
340     case 0x48: /* FifoCnt */  in pl181_read()
349             s->linux_hack = 0;  in pl181_read()
354     case 0x80: case 0x84: case 0x88: case 0x8c: /* FifoData */  in pl181_read()
355     case 0x90: case 0x94: case 0x98: case 0x9c:  in pl181_read()
356     case 0xa0: case 0xa4: case 0xa8: case 0xac:  in pl181_read()
357     case 0xb0: case 0xb4: case 0xb8: case 0xbc:  in pl181_read()
358         if (s->fifo_len == 0) {  in pl181_read()
360             return 0;  in pl181_read()
372         return 0;  in pl181_read()
382     case 0x00: /* Power */  in pl181_write()
383         s->power = value & 0xff;  in pl181_write()
385     case 0x04: /* Clock */  in pl181_write()
386         s->clock = value & 0xff;  in pl181_write()
388     case 0x08: /* Argument */  in pl181_write()
391     case 0x0c: /* Command */  in pl181_write()
408     case 0x24: /* DataTimer */  in pl181_write()
411     case 0x28: /* DataLength */  in pl181_write()
412         s->datalength = value & 0xffff;  in pl181_write()
414     case 0x2c: /* DataCtrl */  in pl181_write()
415         s->datactrl = value & 0xff;  in pl181_write()
421     case 0x38: /* Clear */  in pl181_write()
422         s->status &= ~(value & 0x7ff);  in pl181_write()
424     case 0x3c: /* Mask0 */  in pl181_write()
425         s->mask[0] = value;  in pl181_write()
427     case 0x40: /* Mask1 */  in pl181_write()
430     case 0x80: case 0x84: case 0x88: case 0x8c: /* FifoData */  in pl181_write()
431     case 0x90: case 0x94: case 0x98: case 0x9c:  in pl181_write()
432     case 0xa0: case 0xa4: case 0xa8: case 0xac:  in pl181_write()
433     case 0xb0: case 0xb4: case 0xb8: case 0xbc:  in pl181_write()
434         if (s->datacnt == 0) {  in pl181_write()
472     s->power = 0;  in pl181_reset()
473     s->cmdarg = 0;  in pl181_reset()
474     s->cmd = 0;  in pl181_reset()
475     s->datatimer = 0;  in pl181_reset()
476     s->datalength = 0;  in pl181_reset()
477     s->respcmd = 0;  in pl181_reset()
478     s->response[0] = 0;  in pl181_reset()
479     s->response[1] = 0;  in pl181_reset()
480     s->response[2] = 0;  in pl181_reset()
481     s->response[3] = 0;  in pl181_reset()
482     s->datatimer = 0;  in pl181_reset()
483     s->datalength = 0;  in pl181_reset()
484     s->datactrl = 0;  in pl181_reset()
485     s->datacnt = 0;  in pl181_reset()
486     s->status = 0;  in pl181_reset()
487     s->linux_hack = 0;  in pl181_reset()
488     s->mask[0] = 0;  in pl181_reset()
489     s->mask[1] = 0;  in pl181_reset()
502     memory_region_init_io(&s->iomem, obj, &pl181_ops, s, "pl181", 0x1000);  in pl181_init()
504     sysbus_init_irq(sbd, &s->irq[0]);  in pl181_init()