hw/rx/rx62n.c

38 #define RX62N_IRAM_BASE     0x00000000
39 #define RX62N_DFLASH_BASE   0x00100000
40 #define RX62N_CFLASH_BASE   0xfff80000
46 #define RX62N_ICU_BASE  0x00087000
47 #define RX62N_TMR_BASE  0x00088200
48 #define RX62N_CMT_BASE  0x00088000
49 #define RX62N_SCI_BASE  0x00088240
79  * 0x00 - 0x91: IPR no (IPR00 to IPR91)
80  * 0xff: IPR not assigned
84     0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
85     0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 15 */
86     0x00, 0xff, 0xff, 0xff, 0xff, 0x01, 0xff, 0x02,
87     0xff, 0xff, 0xff, 0x03, 0x04, 0x05, 0x06, 0x07, /* 31 */
88     0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
89     0x10, 0x11, 0x12, 0x13, 0x14, 0x14, 0x14, 0x14, /* 47 */
90     0x15, 0x15, 0x15, 0x15, 0xff, 0xff, 0xff, 0xff,
91     0x18, 0x18, 0x18, 0x18, 0x18, 0x1d, 0x1e, 0x1f, /* 63 */
92     0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
93     0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, /* 79 */
94     0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
95     0xff, 0xff, 0x3a, 0x3b, 0x3c, 0xff, 0xff, 0xff, /* 95 */
96     0x40, 0xff, 0x44, 0x45, 0xff, 0xff, 0x48, 0xff,
97     0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 111 */
98     0xff, 0xff, 0x51, 0x51, 0x51, 0x51, 0x52, 0x52,
99     0x52, 0x53, 0x53, 0x54, 0x54, 0x55, 0x55, 0x56, /* 127 */
100     0x56, 0x57, 0x57, 0x57, 0x57, 0x58, 0x59, 0x59,
101     0x59, 0x59, 0x5a, 0x5b, 0x5b, 0x5b, 0x5c, 0x5c, /* 143 */
102     0x5c, 0x5c, 0x5d, 0x5d, 0x5d, 0x5e, 0x5e, 0x5f,
103     0x5f, 0x60, 0x60, 0x61, 0x61, 0x62, 0x62, 0x62, /* 159 */
104     0x62, 0x63, 0x64, 0x64, 0x64, 0x64, 0x65, 0x66,
105     0x66, 0x66, 0x67, 0x67, 0x67, 0x67, 0x68, 0x68, /* 175 */
106     0x68, 0x69, 0x69, 0x69, 0x6a, 0x6a, 0x6a, 0x6b,
107     0x6b, 0x6b, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 191 */
108     0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x70, 0x71,
109     0x72, 0x73, 0x74, 0x75, 0xff, 0xff, 0xff, 0xff, /* 207 */
110     0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x80, 0x80,
111     0x80, 0x80, 0x81, 0x81, 0x81, 0x81, 0x82, 0x82, /* 223 */
112     0x82, 0x82, 0x83, 0x83, 0x83, 0x83, 0xff, 0xff,
113     0xff, 0xff, 0x85, 0x85, 0x85, 0x85, 0x86, 0x86, /* 239 */
114     0x86, 0x86, 0xff, 0xff, 0xff, 0xff, 0x88, 0x89,
115     0x8a, 0x8b, 0x8c, 0x8d, 0x8e, 0x8f, 0x90, 0x91, /* 255 */
141     for (i = 0; i < NR_IRQS; i++) {  in register_icu()
147     for (i = 0; i < ARRAY_SIZE(levelirq); i++) {  in register_icu()
153     sysbus_connect_irq(icu, 0, qdev_get_gpio_in(DEVICE(&s->cpu), RX_CPU_IRQ));  in register_icu()
156     sysbus_mmio_map(icu, 0, RX62N_ICU_BASE);  in register_icu()
171     for (i = 0; i < TMR_NR_IRQ; i++) {  in register_tmr()
175     sysbus_mmio_map(tmr, 0, RX62N_TMR_BASE + unit * 0x10);  in register_tmr()
190     for (i = 0; i < CMT_NR_IRQ; i++) {  in register_cmt()
194     sysbus_mmio_map(cmt, 0, RX62N_CMT_BASE + unit * 0x10);  in register_cmt()
210     for (i = 0; i < SCI_NR_IRQ; i++) {  in register_sci()
214     sysbus_mmio_map(sci, 0, RX62N_SCI_BASE + unit * 0x08);  in register_sci()
222     if (s->xtal_freq_hz == 0) {  in rx62n_realize()
252     s->cpu.env.ack = qdev_get_gpio_in_named(DEVICE(&s->icu), "ack", 0);  in rx62n_realize()
253     register_tmr(s, 0);  in rx62n_realize()
255     register_cmt(s, 0);  in rx62n_realize()
257     register_sci(s, 0);  in rx62n_realize()
264     DEFINE_PROP_UINT32("xtal-frequency-hz", RX62NState, xtal_freq_hz, 0),