100         memmap[IBEX_DEV_RAM].base, machine->ram);  in opentitan_machine_init()
103         hwaddr firmware_load_addr = memmap[IBEX_DEV_RAM].base;  in opentitan_machine_init()
110                           memmap[IBEX_DEV_RAM].base,  in opentitan_machine_init()
167         memmap[IBEX_DEV_ROM].base, &s->rom);  in lowrisc_ibex_soc_realize()
175     memory_region_add_subregion(sys_mem, memmap[IBEX_DEV_FLASH].base,  in lowrisc_ibex_soc_realize()
177     memory_region_add_subregion(sys_mem, memmap[IBEX_DEV_FLASH_VIRTUAL].base,  in lowrisc_ibex_soc_realize()
184     qdev_prop_set_uint32(DEVICE(&s->plic), "pending-base", 0x1000);  in lowrisc_ibex_soc_realize()
185     qdev_prop_set_uint32(DEVICE(&s->plic), "enable-base", 0x2000);  in lowrisc_ibex_soc_realize()
187     qdev_prop_set_uint32(DEVICE(&s->plic), "context-base", 0x200000);  in lowrisc_ibex_soc_realize()
194     sysbus_mmio_map(SYS_BUS_DEVICE(&s->plic), 0, memmap[IBEX_DEV_PLIC].base);  in lowrisc_ibex_soc_realize()
208     sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart), 0, memmap[IBEX_DEV_UART].base);  in lowrisc_ibex_soc_realize()
225     sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer), 0, memmap[IBEX_DEV_TIMER].base);  in lowrisc_ibex_soc_realize()
240         sysbus_mmio_map(busdev, 0, memmap[IBEX_DEV_SPI_HOST0 + i].base);  in lowrisc_ibex_soc_realize()
259         memmap[IBEX_DEV_GPIO].base, memmap[IBEX_DEV_GPIO].size);  in lowrisc_ibex_soc_realize()
261         memmap[IBEX_DEV_SPI_DEVICE].base, memmap[IBEX_DEV_SPI_DEVICE].size);  in lowrisc_ibex_soc_realize()
263         memmap[IBEX_DEV_I2C].base, memmap[IBEX_DEV_I2C].size);  in lowrisc_ibex_soc_realize()
265         memmap[IBEX_DEV_PATTGEN].base, memmap[IBEX_DEV_PATTGEN].size);  in lowrisc_ibex_soc_realize()
267         memmap[IBEX_DEV_SENSOR_CTRL].base, memmap[IBEX_DEV_SENSOR_CTRL].size);  in lowrisc_ibex_soc_realize()
269         memmap[IBEX_DEV_OTP_CTRL].base, memmap[IBEX_DEV_OTP_CTRL].size);  in lowrisc_ibex_soc_realize()
271         memmap[IBEX_DEV_LC_CTRL].base, memmap[IBEX_DEV_LC_CTRL].size);  in lowrisc_ibex_soc_realize()
273         memmap[IBEX_DEV_PWRMGR].base, memmap[IBEX_DEV_PWRMGR].size);  in lowrisc_ibex_soc_realize()
275         memmap[IBEX_DEV_RSTMGR].base, memmap[IBEX_DEV_RSTMGR].size);  in lowrisc_ibex_soc_realize()
277         memmap[IBEX_DEV_CLKMGR].base, memmap[IBEX_DEV_CLKMGR].size);  in lowrisc_ibex_soc_realize()
279         memmap[IBEX_DEV_PINMUX].base, memmap[IBEX_DEV_PINMUX].size);  in lowrisc_ibex_soc_realize()
281         memmap[IBEX_DEV_AON_TIMER].base, memmap[IBEX_DEV_AON_TIMER].size);  in lowrisc_ibex_soc_realize()
283         memmap[IBEX_DEV_USBDEV].base, memmap[IBEX_DEV_USBDEV].size);  in lowrisc_ibex_soc_realize()
285         memmap[IBEX_DEV_FLASH_CTRL].base, memmap[IBEX_DEV_FLASH_CTRL].size);  in lowrisc_ibex_soc_realize()
287         memmap[IBEX_DEV_AES].base, memmap[IBEX_DEV_AES].size);  in lowrisc_ibex_soc_realize()
289         memmap[IBEX_DEV_HMAC].base, memmap[IBEX_DEV_HMAC].size);  in lowrisc_ibex_soc_realize()
291         memmap[IBEX_DEV_KMAC].base, memmap[IBEX_DEV_KMAC].size);  in lowrisc_ibex_soc_realize()
293         memmap[IBEX_DEV_KEYMGR].base, memmap[IBEX_DEV_KEYMGR].size);  in lowrisc_ibex_soc_realize()
295         memmap[IBEX_DEV_CSRNG].base, memmap[IBEX_DEV_CSRNG].size);  in lowrisc_ibex_soc_realize()
297         memmap[IBEX_DEV_ENTROPY].base, memmap[IBEX_DEV_ENTROPY].size);  in lowrisc_ibex_soc_realize()
299         memmap[IBEX_DEV_EDNO].base, memmap[IBEX_DEV_EDNO].size);  in lowrisc_ibex_soc_realize()
301         memmap[IBEX_DEV_EDN1].base, memmap[IBEX_DEV_EDN1].size);  in lowrisc_ibex_soc_realize()
303         memmap[IBEX_DEV_ALERT_HANDLER].base, memmap[IBEX_DEV_ALERT_HANDLER].size);  in lowrisc_ibex_soc_realize()
305         memmap[IBEX_DEV_SRAM_CTRL].base, memmap[IBEX_DEV_SRAM_CTRL].size);  in lowrisc_ibex_soc_realize()
307         memmap[IBEX_DEV_OTBN].base, memmap[IBEX_DEV_OTBN].size);  in lowrisc_ibex_soc_realize()
309         memmap[IBEX_DEV_IBEX_CFG].base, memmap[IBEX_DEV_IBEX_CFG].size);  in lowrisc_ibex_soc_realize()