10  * SPDX-License-Identifier: GPL-2.0-or-later
24 #include "hw/char/serial-mm.h"
25 #include "system/address-spaces.h"
30 #define MEMORY_BASEADDR 0x80000000
31 #define INTC_BASEADDR 0x41200000
32 #define TIMER_BASEADDR 0x41c00000
33 #define TIMER_BASEADDR2 0x41c10000
34 #define UARTLITE_BASEADDR 0x40600000
35 #define ETHLITE_BASEADDR 0x40e00000
36 #define UART16550_BASEADDR 0x44a10000
37 #define AXIENET_BASEADDR 0x40c00000
38 #define AXIDMA_BASEADDR 0x41e00000
39 #define GPIO_BASEADDR 0x40000000
40 #define GPIO_BASEADDR2 0x40010000
41 #define GPIO_BASEADDR3 0x40020000
42 #define I2C_BASEADDR 0x40800000
43 #define QSPI_BASEADDR 0x44a00000
45 #define TIMER_IRQ           0
56     ram_addr_t ram_size = machine->ram_size;  in mb_v_generic_init()
57     DeviceState *dev, *dma, *eth0;  in mb_v_generic_init()  local
67     cpu = RISCV_CPU(object_new(machine->cpu_type));  in mb_v_generic_init()
75     memory_region_add_subregion(sysmem, 0x00000000, phys_lmb_bram);  in mb_v_generic_init()
81     dev = qdev_new("xlnx.xps-intc");  in mb_v_generic_init()
82     qdev_prop_set_enum(dev, "endianness", ENDIAN_MODE_LITTLE);  in mb_v_generic_init()
83     qdev_prop_set_uint32(dev, "kind-of-intr",  in mb_v_generic_init()
85     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);  in mb_v_generic_init()
86     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, INTC_BASEADDR);  in mb_v_generic_init()
87     sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,  in mb_v_generic_init()
89     for (i = 0; i < 32; i++) {  in mb_v_generic_init()
90         irq[i] = qdev_get_gpio_in(dev, i);  in mb_v_generic_init()
94     dev = qdev_new(TYPE_XILINX_UARTLITE);  in mb_v_generic_init()
95     qdev_prop_set_enum(dev, "endianness", ENDIAN_MODE_LITTLE);  in mb_v_generic_init()
96     qdev_prop_set_chr(dev, "chardev", serial_hd(0));  in mb_v_generic_init()
97     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);  in mb_v_generic_init()
98     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, UARTLITE_BASEADDR);  in mb_v_generic_init()
99     sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[UARTLITE_IRQ]);  in mb_v_generic_init()
102     serial_mm_init(sysmem, UART16550_BASEADDR + 0x1000, 2,  in mb_v_generic_init()
106     /* 2 timers at irq 0 @ 100 Mhz.  */  in mb_v_generic_init()
107     dev = qdev_new("xlnx.xps-timer");  in mb_v_generic_init()
108     qdev_prop_set_enum(dev, "endianness", ENDIAN_MODE_LITTLE);  in mb_v_generic_init()
109     qdev_prop_set_uint32(dev, "one-timer-only", 0);  in mb_v_generic_init()
110     qdev_prop_set_uint32(dev, "clock-frequency", 100000000);  in mb_v_generic_init()
111     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);  in mb_v_generic_init()
112     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, TIMER_BASEADDR);  in mb_v_generic_init()
113     sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[TIMER_IRQ]);  in mb_v_generic_init()
116     dev = qdev_new("xlnx.xps-timer");  in mb_v_generic_init()
117     qdev_prop_set_enum(dev, "endianness", ENDIAN_MODE_LITTLE);  in mb_v_generic_init()
118     qdev_prop_set_uint32(dev, "one-timer-only", 0);  in mb_v_generic_init()
119     qdev_prop_set_uint32(dev, "clock-frequency", 100000000);  in mb_v_generic_init()
120     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);  in mb_v_generic_init()
121     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, TIMER_BASEADDR2);  in mb_v_generic_init()
122     sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[TIMER_IRQ2]);  in mb_v_generic_init()
125     dev = qdev_new("xlnx.xps-ethernetlite");  in mb_v_generic_init()
126     qdev_prop_set_enum(dev, "endianness", ENDIAN_MODE_LITTLE);  in mb_v_generic_init()
127     qemu_configure_nic_device(dev, true, NULL);  in mb_v_generic_init()
128     qdev_prop_set_uint32(dev, "tx-ping-pong", 0);  in mb_v_generic_init()
129     qdev_prop_set_uint32(dev, "rx-ping-pong", 0);  in mb_v_generic_init()
130     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);  in mb_v_generic_init()
131     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, ETHLITE_BASEADDR);  in mb_v_generic_init()
132     sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[ETHLITE_IRQ]);  in mb_v_generic_init()
135     eth0 = qdev_new("xlnx.axi-ethernet");  in mb_v_generic_init()
136     dma = qdev_new("xlnx.axi-dma");  in mb_v_generic_init()
139     object_property_add_child(qdev_get_machine(), "xilinx-eth", OBJECT(eth0));  in mb_v_generic_init()
140     object_property_add_child(qdev_get_machine(), "xilinx-dma", OBJECT(dma));  in mb_v_generic_init()
143                                   "axistream-connected-target", NULL);  in mb_v_generic_init()
145                                   "axistream-control-connected-target", NULL);  in mb_v_generic_init()
147     qdev_prop_set_uint32(eth0, "rxmem", 0x1000);  in mb_v_generic_init()
148     qdev_prop_set_uint32(eth0, "txmem", 0x1000);  in mb_v_generic_init()
149     object_property_set_link(OBJECT(eth0), "axistream-connected", ds,  in mb_v_generic_init()
151     object_property_set_link(OBJECT(eth0), "axistream-control-connected", cs,  in mb_v_generic_init()
154     sysbus_mmio_map(SYS_BUS_DEVICE(eth0), 0, AXIENET_BASEADDR);  in mb_v_generic_init()
155     sysbus_connect_irq(SYS_BUS_DEVICE(eth0), 0, irq[AXIENET_IRQ]);  in mb_v_generic_init()
158                                   "axistream-connected-target", NULL);  in mb_v_generic_init()
160                                   "axistream-control-connected-target", NULL);  in mb_v_generic_init()
162     object_property_set_link(OBJECT(dma), "axistream-connected", ds,  in mb_v_generic_init()
164     object_property_set_link(OBJECT(dma), "axistream-control-connected", cs,  in mb_v_generic_init()
167     sysbus_mmio_map(SYS_BUS_DEVICE(dma), 0, AXIDMA_BASEADDR);  in mb_v_generic_init()
168     sysbus_connect_irq(SYS_BUS_DEVICE(dma), 0, irq[AXIDMA_IRQ0]);  in mb_v_generic_init()
172     create_unimplemented_device("gpio", GPIO_BASEADDR, 0x10000);  in mb_v_generic_init()
173     create_unimplemented_device("gpio2", GPIO_BASEADDR2, 0x10000);  in mb_v_generic_init()
174     create_unimplemented_device("gpio3", GPIO_BASEADDR3, 0x10000);  in mb_v_generic_init()
175     create_unimplemented_device("i2c", I2C_BASEADDR, 0x10000);  in mb_v_generic_init()
176     create_unimplemented_device("qspi", QSPI_BASEADDR, 0x10000);  in mb_v_generic_init()
181     mc->desc = "AMD Microblaze-V generic platform";  in mb_v_generic_machine_init()
182     mc->init = mb_v_generic_init;  in mb_v_generic_machine_init()
183     mc->min_cpus = 1;  in mb_v_generic_machine_init()
184     mc->max_cpus = 1;  in mb_v_generic_machine_init()
185     mc->default_cpu_type = TYPE_RISCV_CPU_BASE;  in mb_v_generic_machine_init()
186     mc->default_cpus = 1;  in mb_v_generic_machine_init()
189 DEFINE_MACHINE("amd-microblaze-v-generic", mb_v_generic_machine_init)