25 #include "hw/qdev-properties.h"
32  * Most register and command definitions come from skiboot.
39  *   Reg 0 - 3 : Host to send command packets to SBE
40  *   Reg 4 - 7 : SBE to send response packets to Host
59  * the SBE about a waiting message in the Host/SBE mailbox registers
64  * Doorbell register for host bridge interrupt. Set by the SBE to inform
65  * host about a response message in the Host/SBE mailbox registers
131     sbe->host_doorbell = val;  in pnv_sbe_set_host_doorbell()
134     qemu_set_irq(sbe->psi_irq, !!val);  in pnv_sbe_set_host_doorbell()
145 /* SBE MBOX command class */
158  *   - xx : command class
159  *   - yy : command
162  * command class and command.
202     pnv_sbe_set_host_doorbell(sbe, sbe->host_doorbell | SBE_HOST_TIMER_EXPIRY);  in sbe_timer()
214         msg.reg[i] = sbe->mbox[i];  in do_sbe_msg()
224         pnv_sbe_set_host_doorbell(sbe, sbe->host_doorbell | SBE_HOST_MSG_READ);  in do_sbe_msg()
232             timer_mod(sbe->timer, qemu_clock_get_us(QEMU_CLOCK_VIRTUAL) + us);  in do_sbe_msg()
236             timer_del(sbe->timer);  in do_sbe_msg()
240         qemu_log_mask(LOG_UNIMP, "SBE Unimplemented command: 0x%x\n", cmd);  in do_sbe_msg()
247     sbe->sbe_doorbell = val;  in pnv_sbe_set_sbe_doorbell()
250         sbe->sbe_doorbell &= ~HOST_SBE_MSG_WAITING;  in pnv_sbe_set_sbe_doorbell()
263         uint32_t idx = offset - PSU_HOST_SBE_MBOX_REG0;  in pnv_sbe_power9_xscom_mbox_read()
264         val = sbe->mbox[idx];  in pnv_sbe_power9_xscom_mbox_read()
268             val = sbe->sbe_doorbell;  in pnv_sbe_power9_xscom_mbox_read()
271             val = sbe->host_doorbell;  in pnv_sbe_power9_xscom_mbox_read()
293         uint32_t idx = offset - PSU_HOST_SBE_MBOX_REG0;  in pnv_sbe_power9_xscom_mbox_write()
294         sbe->mbox[idx] = val;  in pnv_sbe_power9_xscom_mbox_write()
301             pnv_sbe_set_sbe_doorbell(sbe, sbe->sbe_doorbell & val);  in pnv_sbe_power9_xscom_mbox_write()
304             pnv_sbe_set_sbe_doorbell(sbe, sbe->sbe_doorbell | val);  in pnv_sbe_power9_xscom_mbox_write()
311             pnv_sbe_set_host_doorbell(sbe, sbe->host_doorbell & val);  in pnv_sbe_power9_xscom_mbox_write()
314             pnv_sbe_set_host_doorbell(sbe, sbe->host_doorbell | val);  in pnv_sbe_power9_xscom_mbox_write()
339     dc->desc = "PowerNV SBE Controller (POWER9)";  in pnv_sbe_power9_class_init()
340     psc->xscom_ctrl_size = PNV9_XSCOM_SBE_CTRL_SIZE;  in pnv_sbe_power9_class_init()
341     psc->xscom_ctrl_ops = &pnv_sbe_power9_xscom_ctrl_ops;  in pnv_sbe_power9_class_init()
342     psc->xscom_mbox_size = PNV9_XSCOM_SBE_MBOX_SIZE;  in pnv_sbe_power9_class_init()
343     psc->xscom_mbox_ops = &pnv_sbe_power9_xscom_mbox_ops;  in pnv_sbe_power9_class_init()
358     dc->desc = "PowerNV SBE Controller (POWER10)";  in pnv_sbe_power10_class_init()
359     psc->xscom_ctrl_size = PNV10_XSCOM_SBE_CTRL_SIZE;  in pnv_sbe_power10_class_init()
360     psc->xscom_ctrl_ops = &pnv_sbe_power9_xscom_ctrl_ops;  in pnv_sbe_power10_class_init()
361     psc->xscom_mbox_size = PNV10_XSCOM_SBE_MBOX_SIZE;  in pnv_sbe_power10_class_init()
362     psc->xscom_mbox_ops = &pnv_sbe_power9_xscom_mbox_ops;  in pnv_sbe_power10_class_init()
377     pnv_xscom_region_init(&sbe->xscom_ctrl_regs, OBJECT(dev),  in pnv_sbe_realize()
378                           psc->xscom_ctrl_ops, sbe, "xscom-sbe-ctrl",  in pnv_sbe_realize()
379                           psc->xscom_ctrl_size);  in pnv_sbe_realize()
380     pnv_xscom_region_init(&sbe->xscom_mbox_regs, OBJECT(dev),  in pnv_sbe_realize()
381                           psc->xscom_mbox_ops, sbe, "xscom-sbe-mbox",  in pnv_sbe_realize()
382                           psc->xscom_mbox_size);  in pnv_sbe_realize()
384     qdev_init_gpio_out(dev, &sbe->psi_irq, 1);  in pnv_sbe_realize()
386     sbe->timer = timer_new_us(QEMU_CLOCK_VIRTUAL, sbe_timer, sbe);  in pnv_sbe_realize()
393     dc->realize = pnv_sbe_realize;  in pnv_sbe_class_init()
394     dc->desc = "PowerNV SBE Controller";  in pnv_sbe_class_init()
395     dc->user_creatable = false;  in pnv_sbe_class_init()