Lines Matching refs:psi
129 static void pnv_psi_set_bar(PnvPsi *psi, uint64_t bar) in pnv_psi_set_bar() argument
131 PnvPsiClass *ppc = PNV_PSI_GET_CLASS(psi); in pnv_psi_set_bar()
133 uint64_t old = psi->regs[PSIHB_XSCOM_BAR]; in pnv_psi_set_bar()
135 psi->regs[PSIHB_XSCOM_BAR] = bar & (ppc->bar_mask | PSIHB_BAR_EN); in pnv_psi_set_bar()
139 memory_region_del_subregion(sysmem, &psi->regs_mr); in pnv_psi_set_bar()
145 memory_region_add_subregion(sysmem, addr, &psi->regs_mr); in pnv_psi_set_bar()
149 static void pnv_psi_update_fsp_mr(PnvPsi *psi) in pnv_psi_update_fsp_mr() argument
154 static void pnv_psi_set_cr(PnvPsi *psi, uint64_t cr) in pnv_psi_set_cr() argument
156 uint64_t old = psi->regs[PSIHB_XSCOM_CR]; in pnv_psi_set_cr()
158 psi->regs[PSIHB_XSCOM_CR] = cr; in pnv_psi_set_cr()
161 if ((old ^ psi->regs[PSIHB_XSCOM_CR]) & PSIHB_CR_FSP_MMIO_ENABLE) { in pnv_psi_set_cr()
162 pnv_psi_update_fsp_mr(psi); in pnv_psi_set_cr()
166 static void pnv_psi_set_irsn(PnvPsi *psi, uint64_t val) in pnv_psi_set_irsn() argument
168 ICSState *ics = &PNV8_PSI(psi)->ics; in pnv_psi_set_irsn()
175 psi->regs[PSIHB_XSCOM_IRSN] = val & (PSIHB_IRSN_COMP_MSK | in pnv_psi_set_irsn()
220 PnvPsi *psi = opaque; in pnv_psi_power8_set_irq() local
229 src = (psi->regs[xivr_reg] & PSIHB_XIVR_SRC_MSK) >> PSIHB_XIVR_SRC_SH; in pnv_psi_power8_set_irq()
231 psi->regs[stat_reg] |= stat_bits[irq]; in pnv_psi_power8_set_irq()
235 qemu_irq_raise(psi->qirqs[src]); in pnv_psi_power8_set_irq()
237 psi->regs[stat_reg] &= ~stat_bits[irq]; in pnv_psi_power8_set_irq()
241 !(psi->regs[stat_reg] & (PSIHB_CR_PSI_IRQ | PSIHB_CR_FSP_IRQ))) { in pnv_psi_power8_set_irq()
242 qemu_irq_lower(psi->qirqs[src]); in pnv_psi_power8_set_irq()
259 masked = (psi->regs[xivr_reg] & PSIHB_XIVR_PRIO_MSK) == PSIHB_XIVR_PRIO_MSK; in pnv_psi_power8_set_irq()
261 psi->regs[xivr_reg] |= PSIHB_XIVR_PENDING; in pnv_psi_power8_set_irq()
263 psi->regs[xivr_reg] &= ~PSIHB_XIVR_PENDING; in pnv_psi_power8_set_irq()
267 static void pnv_psi_set_xivr(PnvPsi *psi, uint32_t reg, uint64_t val) in pnv_psi_set_xivr() argument
269 ICSState *ics = &PNV8_PSI(psi)->ics; in pnv_psi_set_xivr()
274 psi->regs[reg] = (psi->regs[reg] & PSIHB_XIVR_PENDING) | in pnv_psi_set_xivr()
278 val = psi->regs[reg]; in pnv_psi_set_xivr()
289 if ((psi->regs[reg] & PSIHB_XIVR_PRIO_MSK) == PSIHB_XIVR_PRIO_MSK) { in pnv_psi_set_xivr()
290 psi->regs[reg] &= ~PSIHB_XIVR_PENDING; in pnv_psi_set_xivr()
308 static uint64_t pnv_psi_reg_read(PnvPsi *psi, uint32_t offset, bool mmio) in pnv_psi_reg_read() argument
329 val = psi->regs[offset]; in pnv_psi_reg_read()
337 static void pnv_psi_reg_write(PnvPsi *psi, uint32_t offset, uint64_t val, in pnv_psi_reg_write() argument
346 psi->regs[offset] = val; in pnv_psi_reg_write()
349 psi->regs[PSIHB_XSCOM_FIR_RW] |= val; in pnv_psi_reg_write()
352 psi->regs[PSIHB_XSCOM_FIR_RW] &= val; in pnv_psi_reg_write()
357 pnv_psi_set_bar(psi, val); in pnv_psi_reg_write()
363 psi->regs[PSIHB_XSCOM_FSPBAR] = val & PSIHB_FSPBAR_MASK; in pnv_psi_reg_write()
364 pnv_psi_update_fsp_mr(psi); in pnv_psi_reg_write()
367 pnv_psi_set_cr(psi, val); in pnv_psi_reg_write()
370 pnv_psi_set_cr(psi, psi->regs[PSIHB_XSCOM_CR] | val); in pnv_psi_reg_write()
373 pnv_psi_set_cr(psi, psi->regs[PSIHB_XSCOM_CR] & ~val); in pnv_psi_reg_write()
381 pnv_psi_set_xivr(psi, offset, val); in pnv_psi_reg_write()
388 pnv_psi_set_irsn(psi, val); in pnv_psi_reg_write()
451 PnvPsi *psi = PNV_PSI(dev); in pnv_psi_reset() local
453 memset(psi->regs, 0x0, sizeof(psi->regs)); in pnv_psi_reset()
455 psi->regs[PSIHB_XSCOM_BAR] = psi->bar | PSIHB_BAR_EN; in pnv_psi_reset()
465 PnvPsi *psi = PNV_PSI(dev); in pnv_psi_realize() local
468 pnv_psi_set_bar(psi, psi->bar | PSIHB_BAR_EN); in pnv_psi_realize()
493 PnvPsi *psi = PNV_PSI(dev); in pnv_psi_power8_realize() local
494 ICSState *ics = &PNV8_PSI(psi)->ics; in pnv_psi_power8_realize()
512 psi->qirqs = qemu_allocate_irqs(ics_set_irq, ics, ics->nr_irqs); in pnv_psi_power8_realize()
515 pnv_xscom_region_init(&psi->xscom_regs, OBJECT(dev), &pnv_psi_xscom_ops, in pnv_psi_power8_realize()
516 psi, "xscom-psi", PNV_XSCOM_PSIHB_SIZE); in pnv_psi_power8_realize()
519 memory_region_init_io(&psi->regs_mr, OBJECT(dev), &psi_mmio_ops, psi, in pnv_psi_power8_realize()
525 psi->regs[xivr] = PSIHB_XIVR_PRIO_MSK | in pnv_psi_power8_realize()
650 PnvPsi *psi = PNV_PSI(xf); in pnv_psi_notify() local
651 uint64_t notif_port = psi->regs[PSIHB_REG(PSIHB9_ESB_NOTIF_ADDR)]; in pnv_psi_notify()
656 (psi->regs[PSIHB_REG(PSIHB9_IVT_OFFSET)] >> PSIHB9_IVT_OFF_SHIFT); in pnv_psi_notify()
679 PnvPsi *psi = PNV_PSI(opaque); in pnv_psi_p9_mmio_read() local
691 val = psi->regs[reg]; in pnv_psi_p9_mmio_read()
703 PnvPsi *psi = PNV_PSI(opaque); in pnv_psi_p9_mmio_write() local
704 Pnv9Psi *psi9 = PNV9_PSI(psi); in pnv_psi_p9_mmio_write()
724 psi->regs[reg] = val; in pnv_psi_p9_mmio_write()
734 if (psi->regs[reg] & PSIHB9_ESB_CI_VALID) { in pnv_psi_p9_mmio_write()
738 if (!(psi->regs[reg] & PSIHB9_ESB_CI_VALID)) { in pnv_psi_p9_mmio_write()
745 psi->regs[reg] = val; in pnv_psi_p9_mmio_write()
749 psi->regs[reg] = val; in pnv_psi_p9_mmio_write()
752 psi->regs[reg] = val; in pnv_psi_p9_mmio_write()
790 PnvPsi *psi = PNV_PSI(opaque); in pnv_psi_p9_xscom_write() local
797 pnv_psi_set_bar(psi, val); in pnv_psi_p9_xscom_write()
819 PnvPsi *psi = opaque; in pnv_psi_power9_set_irq() local
820 uint64_t irq_method = psi->regs[PSIHB_REG(PSIHB9_INTERRUPT_CONTROL)]; in pnv_psi_power9_set_irq()
829 psi->regs[PSIHB_REG(PSIHB9_IRQ_LEVEL)] |= PPC_BIT(irq); in pnv_psi_power9_set_irq()
831 psi->regs[PSIHB_REG(PSIHB9_IRQ_LEVEL)] &= ~PPC_BIT(irq); in pnv_psi_power9_set_irq()
834 qemu_set_irq(psi->qirqs[irq], state); in pnv_psi_power9_set_irq()
839 Pnv9Psi *psi = PNV9_PSI(dev); in pnv_psi_power9_reset() local
843 if (memory_region_is_mapped(&psi->source.esb_mmio)) { in pnv_psi_power9_reset()
844 memory_region_del_subregion(get_system_memory(), &psi->source.esb_mmio); in pnv_psi_power9_reset()
850 Pnv9Psi *psi = PNV9_PSI(obj); in pnv_psi_power9_instance_init() local
852 object_initialize_child(obj, "source", &psi->source, TYPE_XIVE_SOURCE); in pnv_psi_power9_instance_init()
853 object_property_add_alias(obj, "shift", OBJECT(&psi->source), "shift"); in pnv_psi_power9_instance_init()
858 PnvPsi *psi = PNV_PSI(dev); in pnv_psi_power9_realize() local
859 XiveSource *xsrc = &PNV9_PSI(psi)->source; in pnv_psi_power9_realize()
864 object_property_set_link(OBJECT(xsrc), "xive", OBJECT(psi), &error_abort); in pnv_psi_power9_realize()
875 psi->qirqs = qemu_allocate_irqs(xive_source_set_irq, xsrc, xsrc->nr_irqs); in pnv_psi_power9_realize()
880 pnv_xscom_region_init(&psi->xscom_regs, OBJECT(dev), &pnv_psi_p9_xscom_ops, in pnv_psi_power9_realize()
881 psi, "xscom-psi", PNV9_XSCOM_PSIHB_SIZE); in pnv_psi_power9_realize()
884 memory_region_init_io(&psi->regs_mr, OBJECT(dev), &pnv_psi_p9_mmio_ops, psi, in pnv_psi_power9_realize()
980 PnvPsi *psi = PNV_PSI(psi9); in pnv_psi_pic_print_info() local
983 (psi->regs[PSIHB_REG(PSIHB9_IVT_OFFSET)] >> PSIHB9_IVT_OFF_SHIFT); in pnv_psi_pic_print_info()