Lines Matching +full:- +full:- +full:enable +full:- +full:fdt
4 * Copyright (c) 2022-2023, IBM Corporation.
6 * SPDX-License-Identifier: GPL-2.0-or-later
9 * purpose is to keep time-of-day across chips and cores.
32 #include "hw/qdev-properties.h"
33 #include "hw/ppc/fdt.h"
53 /* -- TOD primary/secondary master/slave control register -- */
56 /* -- TOD primary/secondary master/slave status register -- */
64 #define TOD_TX_TTYPE_2_REG 0x00000013 /* Enable step checkers */
78 /* -- TOD Error interrupt register -- */
86 * - The reset state is 0 error.
87 * - A hardware error detected will transition to state 0 from any state.
88 * - LOAD_TOD_MOD and TTYPE5 will transition to state 7 from any state.
91 * |------------+------------------------------+-----|
94 * | 7 not_set | LOAD_TOD (bit-63 = 0) | 2 |
95 * | 7 not_set | LOAD_TOD (bit-63 = 1) | 1 |
120 if (chiptod->tod_state == tod_running) { in pnv_chiptod_xscom_read()
126 if (chiptod->primary) { in pnv_chiptod_xscom_read()
128 } else if (chiptod->secondary) { in pnv_chiptod_xscom_read()
135 val = chiptod->pss_mss_ctrl_reg; in pnv_chiptod_xscom_read()
141 val = chiptod->tod_error; in pnv_chiptod_xscom_read()
144 if (chiptod->tod_state == tod_running) { in pnv_chiptod_xscom_read()
162 if (chiptod->tod_state != tod_not_set) { in chiptod_receive_ttype()
165 chiptod->tod_state); in chiptod_receive_ttype()
167 chiptod->tod_state = tod_running; in chiptod_receive_ttype()
172 chiptod->tod_state = tod_not_set; in chiptod_receive_ttype()
187 for (i = 0; i < pnv->num_chips; i++) { in chiptod_power9_broadcast_ttype()
188 Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]); in chiptod_power9_broadcast_ttype()
189 PnvChipTOD *chiptod = &chip9->chiptod; in chiptod_power9_broadcast_ttype()
203 for (i = 0; i < pnv->num_chips; i++) { in chiptod_power10_broadcast_ttype()
204 Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]); in chiptod_power10_broadcast_ttype()
205 PnvChipTOD *chiptod = &chip10->chiptod; in chiptod_power10_broadcast_ttype()
219 for (i = 0; i < chip->nr_cores; i++) { in pnv_chip_get_core_by_xscom_base()
220 PnvCore *pc = chip->cores[i]; in pnv_chip_get_core_by_xscom_base()
222 int core_hwid = cc->core_id; in pnv_chip_get_core_by_xscom_base()
224 if (pcc->xscom_core_base(chip, core_hwid) == xscom_base) { in pnv_chip_get_core_by_xscom_base()
247 return pnv_chip_get_core_by_xscom_base(chiptod->chip, addr & ~0xfff); in chiptod_power9_tx_ttype_target()
251 return pnv_chip_find_core(chiptod->chip, core_id); in chiptod_power9_tx_ttype_target()
273 * This may not deal with P10 big-core addressing at the moment. in chiptod_power10_tx_ttype_target()
274 * The big-core code in skiboot syncs small cores, but it targets in chiptod_power10_tx_ttype_target()
275 * the even PIR (first small-core) when syncing second small-core. in chiptod_power10_tx_ttype_target()
277 return pnv_chip_get_core_by_xscom_base(chiptod->chip, addr & ~0xfff); in chiptod_power10_tx_ttype_target()
298 if (chiptod->primary) { in pnv_chiptod_xscom_write()
303 val |= PPC_BIT(2); /* Drawer is master (don't simulate multi-drawer) */ in pnv_chiptod_xscom_write()
304 chiptod->pss_mss_ctrl_reg = val & PPC_BITMASK(0, 31); in pnv_chiptod_xscom_write()
313 * specifies the SCOM address, and a core-ID mode which uses the in pnv_chiptod_xscom_write()
316 chiptod->slave_pc_target = pctc->tx_ttype_target(chiptod, val); in pnv_chiptod_xscom_write()
317 if (!chiptod->slave_pc_target) { in pnv_chiptod_xscom_write()
324 chiptod->tod_error &= ~val; in pnv_chiptod_xscom_write()
332 chiptod->tod_state = tod_not_set; in pnv_chiptod_xscom_write()
336 if (chiptod->tod_state != tod_not_set) { in pnv_chiptod_xscom_write()
339 chiptod->tod_state); in pnv_chiptod_xscom_write()
342 chiptod->tod_state = tod_stopped; in pnv_chiptod_xscom_write()
344 chiptod->tod_state = tod_running; in pnv_chiptod_xscom_write()
355 if (chiptod->tod_state != tod_running) { in pnv_chiptod_xscom_write()
358 chiptod->tod_state); in pnv_chiptod_xscom_write()
363 } else if (chiptod->slave_pc_target == NULL) { in pnv_chiptod_xscom_write()
367 PnvCore *pc = chiptod->slave_pc_target; in pnv_chiptod_xscom_write()
379 if (pc->tod_state.tb_ready_for_tod) { in pnv_chiptod_xscom_write()
380 pc->tod_state.tod_sent_to_tb = 1; in pnv_chiptod_xscom_write()
389 if (chiptod->tod_state != tod_stopped) { in pnv_chiptod_xscom_write()
392 chiptod->tod_state); in pnv_chiptod_xscom_write()
394 chiptod->tod_state = tod_running; in pnv_chiptod_xscom_write()
399 pctc->broadcast_ttype(chiptod, offset); in pnv_chiptod_xscom_write()
417 static int pnv_chiptod_dt_xscom(PnvXScomInterface *dev, void *fdt, in pnv_chiptod_dt_xscom() argument
431 offset = fdt_add_subnode(fdt, xscom_offset, name); in pnv_chiptod_dt_xscom()
434 if (chiptod->primary) { in pnv_chiptod_dt_xscom()
435 _FDT((fdt_setprop(fdt, offset, "primary", NULL, 0))); in pnv_chiptod_dt_xscom()
436 } else if (chiptod->secondary) { in pnv_chiptod_dt_xscom()
437 _FDT((fdt_setprop(fdt, offset, "secondary", NULL, 0))); in pnv_chiptod_dt_xscom()
440 _FDT((fdt_setprop(fdt, offset, "reg", reg, sizeof(reg)))); in pnv_chiptod_dt_xscom()
441 _FDT((fdt_setprop(fdt, offset, "compatible", compat, compat_size))); in pnv_chiptod_dt_xscom()
445 static int pnv_chiptod_power9_dt_xscom(PnvXScomInterface *dev, void *fdt, in pnv_chiptod_power9_dt_xscom() argument
448 const char compat[] = "ibm,power-chiptod\0ibm,power9-chiptod"; in pnv_chiptod_power9_dt_xscom()
450 return pnv_chiptod_dt_xscom(dev, fdt, xscom_offset, compat, sizeof(compat)); in pnv_chiptod_power9_dt_xscom()
465 dc->desc = "PowerNV ChipTOD Controller (POWER9)"; in pnv_chiptod_power9_class_init()
468 xdc->dt_xscom = pnv_chiptod_power9_dt_xscom; in pnv_chiptod_power9_class_init()
470 pctc->broadcast_ttype = chiptod_power9_broadcast_ttype; in pnv_chiptod_power9_class_init()
471 pctc->tx_ttype_target = chiptod_power9_tx_ttype_target; in pnv_chiptod_power9_class_init()
473 pctc->xscom_size = PNV_XSCOM_CHIPTOD_SIZE; in pnv_chiptod_power9_class_init()
487 static int pnv_chiptod_power10_dt_xscom(PnvXScomInterface *dev, void *fdt, in pnv_chiptod_power10_dt_xscom() argument
490 const char compat[] = "ibm,power-chiptod\0ibm,power10-chiptod"; in pnv_chiptod_power10_dt_xscom()
492 return pnv_chiptod_dt_xscom(dev, fdt, xscom_offset, compat, sizeof(compat)); in pnv_chiptod_power10_dt_xscom()
501 dc->desc = "PowerNV ChipTOD Controller (POWER10)"; in pnv_chiptod_power10_class_init()
504 xdc->dt_xscom = pnv_chiptod_power10_dt_xscom; in pnv_chiptod_power10_class_init()
506 pctc->broadcast_ttype = chiptod_power10_broadcast_ttype; in pnv_chiptod_power10_class_init()
507 pctc->tx_ttype_target = chiptod_power10_tx_ttype_target; in pnv_chiptod_power10_class_init()
509 pctc->xscom_size = PNV_XSCOM_CHIPTOD_SIZE; in pnv_chiptod_power10_class_init()
527 chiptod->pss_mss_ctrl_reg = 0; in pnv_chiptod_reset()
528 if (chiptod->primary) { in pnv_chiptod_reset()
529 chiptod->pss_mss_ctrl_reg |= PPC_BIT(1); /* TOD is master */ in pnv_chiptod_reset()
531 /* Drawer is master (we do not simulate multi-drawer) */ in pnv_chiptod_reset()
532 chiptod->pss_mss_ctrl_reg |= PPC_BIT(2); in pnv_chiptod_reset()
534 chiptod->tod_error = 0; in pnv_chiptod_reset()
535 chiptod->tod_state = tod_error; in pnv_chiptod_reset()
544 pnv_xscom_region_init(&chiptod->xscom_regs, OBJECT(dev), in pnv_chiptod_realize()
545 &pnv_chiptod_xscom_ops, chiptod, "xscom-chiptod", in pnv_chiptod_realize()
546 pctc->xscom_size); in pnv_chiptod_realize()
562 dc->realize = pnv_chiptod_realize; in pnv_chiptod_class_init()
563 dc->unrealize = pnv_chiptod_unrealize; in pnv_chiptod_class_init()
564 dc->desc = "PowerNV ChipTOD Controller"; in pnv_chiptod_class_init()
565 dc->user_creatable = false; in pnv_chiptod_class_init()