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4 * Copyright (c) 2016-2024, IBM Corporation.
6 * SPDX-License-Identifier: GPL-2.0-or-later
45 #include "target/ppc/mmu-hash64.h"
47 #include "hw/pci-host/pnv_phb.h"
48 #include "hw/pci-host/pnv_phb3.h"
49 #include "hw/pci-host/pnv_phb4.h"
52 #include "hw/qdev-properties.h"
58 #include "hw/char/serial-isa.h"
69 #define PNOR_FILE_NAME "pnv-pnor.bin"
79 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX); in pnv_chip_core_typename()
114 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id))); in pnv_dt_memory()
124 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); in get_cpus_node()
125 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); in get_cpus_node()
136 * device tree, used in XSCOM to address cores and in interrupt
141 PowerPCCPU *cpu = pc->threads[0]; in pnv_dt_core()
144 int smt_threads = CPU_CORE(pc)->nr_threads; in pnv_dt_core()
145 CPUPPCState *env = &cpu->env; in pnv_dt_core()
161 pnv_cc->get_pir_tir(chip, pc->hwid, 0, &pir, &tir); in pnv_dt_core()
166 nodename = g_strdup_printf("%s@%x", dc->fw_name, pir); in pnv_dt_core()
171 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id))); in pnv_dt_core()
177 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); in pnv_dt_core()
178 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", in pnv_dt_core()
179 env->dcache_line_size))); in pnv_dt_core()
180 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", in pnv_dt_core()
181 env->dcache_line_size))); in pnv_dt_core()
182 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", in pnv_dt_core()
183 env->icache_line_size))); in pnv_dt_core()
184 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", in pnv_dt_core()
185 env->icache_line_size))); in pnv_dt_core()
187 if (pcc->l1_dcache_size) { in pnv_dt_core()
188 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", in pnv_dt_core()
189 pcc->l1_dcache_size))); in pnv_dt_core()
193 if (pcc->l1_icache_size) { in pnv_dt_core()
194 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", in pnv_dt_core()
195 pcc->l1_icache_size))); in pnv_dt_core()
200 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); in pnv_dt_core()
201 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); in pnv_dt_core()
202 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", in pnv_dt_core()
203 cpu->hash64_opts->slb_size))); in pnv_dt_core()
205 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); in pnv_dt_core()
212 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", in pnv_dt_core()
222 if (env->insns_flags & PPC_ALTIVEC) { in pnv_dt_core()
223 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; in pnv_dt_core()
233 if (env->insns_flags2 & PPC2_DFP) { in pnv_dt_core()
240 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", in pnv_dt_core()
245 if (pc->big_core) { in pnv_dt_core()
248 pnv_cc->get_pir_tir(chip, pc->hwid, i, &pir, NULL); in pnv_dt_core()
251 pnv_cc->get_pir_tir(chip, pc->hwid + 1, i, &pir, NULL); in pnv_dt_core()
254 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", in pnv_dt_core()
260 pnv_cc->get_pir_tir(chip, pc->hwid, i, &pir, NULL); in pnv_dt_core()
263 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", in pnv_dt_core()
278 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp"; in pnv_dt_icp()
283 pcc->get_pir_tir(chip, hwid, 0, &pir, NULL); in pnv_dt_icp()
297 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr); in pnv_dt_icp()
305 "PowerPC-External-Interrupt-Presentation"))); in pnv_dt_icp()
306 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0))); in pnv_dt_icp()
307 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges", in pnv_dt_icp()
309 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1))); in pnv_dt_icp()
310 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0))); in pnv_dt_icp()
322 phb->chip = chip; in pnv_chip_add_phb()
324 chip8->phbs[chip8->num_phbs] = phb; in pnv_chip_add_phb()
325 chip8->num_phbs++; in pnv_chip_add_phb()
342 static const char compat[] = "ibm,power8-xscom\0ibm,xscom"; in pnv_chip_power8_dt_populate()
350 for (i = 0; i < chip->nr_cores; i++) { in pnv_chip_power8_dt_populate()
351 PnvCore *pnv_core = chip->cores[i]; in pnv_chip_power8_dt_populate()
356 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", in pnv_chip_power8_dt_populate()
360 pnv_dt_icp(chip, fdt, pnv_core->hwid, CPU_CORE(pnv_core)->nr_threads); in pnv_chip_power8_dt_populate()
363 if (chip->ram_size) { in pnv_chip_power8_dt_populate()
364 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); in pnv_chip_power8_dt_populate()
374 0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0, /* 0 - 5 */
376 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */
378 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */
380 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 18 - 23 */
382 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */
384 0x00, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */
386 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 36 - 41 */
388 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */
390 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */
392 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */
394 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */
399 static const char compat[] = "ibm,power9-xscom\0ibm,xscom"; in pnv_chip_power9_dt_populate()
407 for (i = 0; i < chip->nr_cores; i++) { in pnv_chip_power9_dt_populate()
408 PnvCore *pnv_core = chip->cores[i]; in pnv_chip_power9_dt_populate()
413 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", in pnv_chip_power9_dt_populate()
416 if (pnv_core->big_core) { in pnv_chip_power9_dt_populate()
417 i++; /* Big-core groups two QEMU cores */ in pnv_chip_power9_dt_populate()
421 if (chip->ram_size) { in pnv_chip_power9_dt_populate()
422 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); in pnv_chip_power9_dt_populate()
435 0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0, /* 0 - 5 */
437 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */
439 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */
441 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */
443 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */
445 0x00, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */
447 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 36 - 41 */
449 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */
451 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */
453 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */
455 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */
457 0x00, 0x00, 0xce, 0x00, 0x00, 0x00, /* 66 - 71 */
459 0x80, 0x00, /* 72 - 73 */
464 static const char compat[] = "ibm,power10-xscom\0ibm,xscom"; in pnv_chip_power10_dt_populate()
472 for (i = 0; i < chip->nr_cores; i++) { in pnv_chip_power10_dt_populate()
473 PnvCore *pnv_core = chip->cores[i]; in pnv_chip_power10_dt_populate()
478 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", in pnv_chip_power10_dt_populate()
481 if (pnv_core->big_core) { in pnv_chip_power10_dt_populate()
482 i++; /* Big-core groups two QEMU cores */ in pnv_chip_power10_dt_populate()
486 if (chip->ram_size) { in pnv_chip_power10_dt_populate()
487 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); in pnv_chip_power10_dt_populate()
495 uint32_t io_base = d->ioport_id; in pnv_dt_rtc()
516 uint32_t io_base = d->ioport_id; in pnv_dt_serial()
537 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200))); in pnv_dt_serial()
538 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200))); in pnv_dt_serial()
540 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", in pnv_dt_serial()
549 const char compatible[] = "bt\0ipmi-bt"; in pnv_dt_ipmi_bt()
553 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */ in pnv_dt_ipmi_bt()
577 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", in pnv_dt_ipmi_bt()
592 pnv_dt_rtc(d, args->fdt, args->offset); in pnv_dt_isa_device()
594 pnv_dt_serial(d, args->fdt, args->offset); in pnv_dt_isa_device()
595 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) { in pnv_dt_isa_device()
596 pnv_dt_ipmi_bt(d, args->fdt, args->offset); in pnv_dt_isa_device()
599 d->ioport_id); in pnv_dt_isa_device()
611 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename); in pnv_dt_isa()
628 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL, in pnv_dt_isa()
637 off = fdt_add_subnode(fdt, off, "power-mgt"); in pnv_dt_power_mgt()
639 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000)); in pnv_dt_power_mgt()
658 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2))); in pnv_dt_create()
659 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2))); in pnv_dt_create()
662 _FDT((fdt_setprop(fdt, 0, "compatible", pmc->compat, pmc->compat_size))); in pnv_dt_create()
667 _FDT((fdt_setprop_string(fdt, 0, "system-id", buf))); in pnv_dt_create()
672 if (machine->kernel_cmdline) { in pnv_dt_create()
674 machine->kernel_cmdline))); in pnv_dt_create()
677 if (pnv->initrd_size) { in pnv_dt_create()
678 uint32_t start_prop = cpu_to_be32(pnv->initrd_base); in pnv_dt_create()
679 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size); in pnv_dt_create()
681 _FDT((fdt_setprop(fdt, off, "linux,initrd-start", in pnv_dt_create()
683 _FDT((fdt_setprop(fdt, off, "linux,initrd-end", in pnv_dt_create()
687 /* Populate device tree for each chip */ in pnv_dt_create()
688 for (i = 0; i < pnv->num_chips; i++) { in pnv_dt_create()
689 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt); in pnv_dt_create()
695 if (pnv->bmc) { in pnv_dt_create()
696 pnv_dt_bmc_sensors(pnv->bmc, fdt); in pnv_dt_create()
700 if (pmc->dt_power_mgt) { in pnv_dt_create()
701 pmc->dt_power_mgt(pnv, fdt); in pnv_dt_create()
711 if (pnv->bmc) { in pnv_powerdown_notify()
712 pnv_bmc_powerdown(pnv->bmc); in pnv_powerdown_notify()
730 if (!pnv->bmc) { in pnv_reset()
733 warn_report("machine has no BMC device. Use '-device " in pnv_reset()
734 "ipmi-bmc-sim,id=bmc0 -device isa-ipmi-bt,bmc=bmc0,irq=10' " in pnv_reset()
738 pnv_bmc_set_pnor(bmc, pnv->pnor); in pnv_reset()
739 pnv->bmc = bmc; in pnv_reset()
743 if (machine->fdt) { in pnv_reset()
744 fdt = machine->fdt; in pnv_reset()
747 /* Pack resulting tree */ in pnv_reset()
753 /* Update machine->fdt with latest fdt */ in pnv_reset()
754 if (machine->fdt != fdt) { in pnv_reset()
756 * Set machine->fdt for 'dumpdtb' QMP/HMP command. Free in pnv_reset()
757 * the existing machine->fdt to avoid leaking it during in pnv_reset()
760 g_free(machine->fdt); in pnv_reset()
761 machine->fdt = fdt; in pnv_reset()
768 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_EXTERNAL); in pnv_chip_power8_isa_create()
770 qdev_connect_gpio_out_named(DEVICE(&chip8->lpc), "LPCHC", 0, irq); in pnv_chip_power8_isa_create()
772 return pnv_lpc_isa_create(&chip8->lpc, true, errp); in pnv_chip_power8_isa_create()
778 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_LPC_I2C); in pnv_chip_power8nvl_isa_create()
780 qdev_connect_gpio_out_named(DEVICE(&chip8->lpc), "LPCHC", 0, irq); in pnv_chip_power8nvl_isa_create()
782 return pnv_lpc_isa_create(&chip8->lpc, false, errp); in pnv_chip_power8nvl_isa_create()
790 irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPCHC); in pnv_chip_power9_isa_create()
791 qdev_connect_gpio_out_named(DEVICE(&chip9->lpc), "LPCHC", 0, irq); in pnv_chip_power9_isa_create()
793 irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPC_SIRQ0); in pnv_chip_power9_isa_create()
794 qdev_connect_gpio_out_named(DEVICE(&chip9->lpc), "SERIRQ", 0, irq); in pnv_chip_power9_isa_create()
795 irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPC_SIRQ1); in pnv_chip_power9_isa_create()
796 qdev_connect_gpio_out_named(DEVICE(&chip9->lpc), "SERIRQ", 1, irq); in pnv_chip_power9_isa_create()
797 irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPC_SIRQ2); in pnv_chip_power9_isa_create()
798 qdev_connect_gpio_out_named(DEVICE(&chip9->lpc), "SERIRQ", 2, irq); in pnv_chip_power9_isa_create()
799 irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPC_SIRQ3); in pnv_chip_power9_isa_create()
800 qdev_connect_gpio_out_named(DEVICE(&chip9->lpc), "SERIRQ", 3, irq); in pnv_chip_power9_isa_create()
802 return pnv_lpc_isa_create(&chip9->lpc, false, errp); in pnv_chip_power9_isa_create()
810 irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPCHC); in pnv_chip_power10_isa_create()
811 qdev_connect_gpio_out_named(DEVICE(&chip10->lpc), "LPCHC", 0, irq); in pnv_chip_power10_isa_create()
813 irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPC_SIRQ0); in pnv_chip_power10_isa_create()
814 qdev_connect_gpio_out_named(DEVICE(&chip10->lpc), "SERIRQ", 0, irq); in pnv_chip_power10_isa_create()
815 irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPC_SIRQ1); in pnv_chip_power10_isa_create()
816 qdev_connect_gpio_out_named(DEVICE(&chip10->lpc), "SERIRQ", 1, irq); in pnv_chip_power10_isa_create()
817 irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPC_SIRQ2); in pnv_chip_power10_isa_create()
818 qdev_connect_gpio_out_named(DEVICE(&chip10->lpc), "SERIRQ", 2, irq); in pnv_chip_power10_isa_create()
819 irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPC_SIRQ3); in pnv_chip_power10_isa_create()
820 qdev_connect_gpio_out_named(DEVICE(&chip10->lpc), "SERIRQ", 3, irq); in pnv_chip_power10_isa_create()
822 return pnv_lpc_isa_create(&chip10->lpc, false, errp); in pnv_chip_power10_isa_create()
827 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp); in pnv_isa_create()
835 ics_pic_print_info(&chip8->psi.ics, buf); in pnv_chip_power8_pic_print_info()
837 for (i = 0; i < chip8->num_phbs; i++) { in pnv_chip_power8_pic_print_info()
838 PnvPHB *phb = chip8->phbs[i]; in pnv_chip_power8_pic_print_info()
839 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); in pnv_chip_power8_pic_print_info()
841 pnv_phb3_msi_pic_print_info(&phb3->msis, buf); in pnv_chip_power8_pic_print_info()
842 ics_pic_print_info(&phb3->lsis, buf); in pnv_chip_power8_pic_print_info()
855 pnv_phb4_pic_print_info(PNV_PHB4(phb->backend), buf); in pnv_chip_power9_pic_print_info_child()
864 pnv_xive_pic_print_info(&chip9->xive, buf); in pnv_chip_power9_pic_print_info()
865 pnv_psi_pic_print_info(&chip9->psi, buf); in pnv_chip_power9_pic_print_info()
895 return ppc_default->pvr_match(ppc_default, ppc->pvr, false); in pnv_match_cpu()
900 ISADevice *dev = isa_new("isa-ipmi-bt"); in pnv_ipmi_bt_init()
911 pnv_xive2_pic_print_info(&chip10->xive, buf); in pnv_chip_power10_pic_print_info()
912 pnv_psi_pic_print_info(&chip10->psi, buf); in pnv_chip_power10_pic_print_info()
923 assert(machine->ram_size >= 1 * GiB); in pnv_chip_get_ram_size()
925 ram_per_chip = machine->ram_size / pnv->num_chips; in pnv_chip_get_ram_size()
930 assert(pnv->num_chips > 1); in pnv_chip_get_ram_size()
932 ram_per_chip = (machine->ram_size - 1 * GiB) / (pnv->num_chips - 1); in pnv_chip_get_ram_size()
938 const char *bios_name = machine->firmware ?: FW_FILE_NAME; in pnv_init()
942 int max_smt_threads = pmc->max_smt_threads; in pnv_init()
953 mc->name); in pnv_init()
958 if (machine->ram_size < mc->default_ram_size) { in pnv_init()
959 char *sz = size_to_str(mc->default_ram_size); in pnv_init()
966 if (machine->dtb && (strlen(machine->kernel_cmdline) != 0)) { in pnv_init()
967 error_report("-append and -dtb cannot be used together, as passed" in pnv_init()
972 memory_region_add_subregion(get_system_memory(), 0, machine->ram); in pnv_init()
985 opts = drive_add(IF_MTD, -1, fw_filename, "format=raw,readonly=on"); in pnv_init()
994 pnv->pnor = PNV_PNOR(dev); in pnv_init()
1003 fw_size = load_image_targphys(fw_filename, pnv->fw_load_addr, FW_MAX_SIZE); in pnv_init()
1011 if (machine->kernel_filename) { in pnv_init()
1014 kernel_size = load_image_targphys(machine->kernel_filename, in pnv_init()
1018 machine->kernel_filename); in pnv_init()
1024 if (machine->initrd_filename) { in pnv_init()
1025 pnv->initrd_base = INITRD_LOAD_ADDR; in pnv_init()
1026 pnv->initrd_size = load_image_targphys(machine->initrd_filename, in pnv_init()
1027 pnv->initrd_base, INITRD_MAX_SIZE); in pnv_init()
1028 if (pnv->initrd_size < 0) { in pnv_init()
1030 machine->initrd_filename); in pnv_init()
1036 if (machine->dtb) { in pnv_init()
1039 warn_report("with manually passed dtb, some options like '-append'" in pnv_init()
1040 " will get ignored and the dtb passed will be used as-is"); in pnv_init()
1042 /* read the file 'machine->dtb', and load it into 'fdt' buffer */ in pnv_init()
1043 machine->fdt = load_device_tree(machine->dtb, &fdt_size); in pnv_init()
1044 if (!machine->fdt) { in pnv_init()
1045 error_report("Could not load dtb '%s'", machine->dtb); in pnv_init()
1057 if (!pnv_match_cpu(mc->default_cpu_type, machine->cpu_type)) { in pnv_init()
1059 machine->cpu_type, mc->name); in pnv_init()
1064 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); in pnv_init()
1066 i, machine->cpu_type); in pnv_init()
1069 i, machine->cpu_type, mc->name); in pnv_init()
1073 /* Set lpar-per-core mode if lpar-per-thread is not supported */ in pnv_init()
1074 if (!pmc->has_lpar_per_thread) { in pnv_init()
1075 pnv->lpar_per_core = true; in pnv_init()
1078 pnv->num_chips = in pnv_init()
1079 machine->smp.max_cpus / (machine->smp.cores * machine->smp.threads); in pnv_init()
1081 if (pnv->big_core) { in pnv_init()
1082 if (machine->smp.threads % 2 == 1) { in pnv_init()
1083 error_report("Cannot support %d threads with big-core option " in pnv_init()
1085 machine->smp.threads); in pnv_init()
1091 if (machine->smp.threads > max_smt_threads) { in pnv_init()
1093 "on %s machine", max_smt_threads, mc->desc); in pnv_init()
1094 if (pmc->max_smt_threads == 4) { in pnv_init()
1095 error_report("(use big-core=on for 8 threads per core)"); in pnv_init()
1100 if (pnv->big_core) { in pnv_init()
1102 * powernv models PnvCore as a SMT4 core. Big-core requires 2xPnvCore in pnv_init()
1104 * device-tree and TCG SMT code make the 2 cores appear as one big core in pnv_init()
1105 * from software point of view. pnv pervasive models and xscoms tend to in pnv_init()
1108 machine->smp.cores *= 2; in pnv_init()
1109 machine->smp.threads /= 2; in pnv_init()
1112 if (!is_power_of_2(machine->smp.threads)) { in pnv_init()
1115 machine->smp.threads); in pnv_init()
1123 if (!is_power_of_2(pnv->num_chips) || pnv->num_chips > 16) { in pnv_init()
1124 error_report("invalid number of chips: '%d'", pnv->num_chips); in pnv_init()
1126 "Try '-smp sockets=N'. Valid values are : 1, 2, 4, 8 and 16.\n"); in pnv_init()
1130 pnv->chips = g_new0(PnvChip *, pnv->num_chips); in pnv_init()
1131 for (i = 0; i < pnv->num_chips; i++) { in pnv_init()
1136 pnv->chips[i] = PNV_CHIP(chip); in pnv_init()
1139 object_property_set_int(chip, "ram-start", chip_ram_start, in pnv_init()
1141 object_property_set_int(chip, "ram-size", chip_ram_size, in pnv_init()
1147 object_property_set_int(chip, "chip-id", i, &error_fatal); in pnv_init()
1148 object_property_set_int(chip, "nr-cores", machine->smp.cores, in pnv_init()
1150 object_property_set_int(chip, "nr-threads", machine->smp.threads, in pnv_init()
1152 object_property_set_bool(chip, "big-core", pnv->big_core, in pnv_init()
1154 object_property_set_bool(chip, "lpar-per-core", pnv->lpar_per_core, in pnv_init()
1164 object_property_set_link(chip, "xive-fabric", OBJECT(pnv), in pnv_init()
1172 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal); in pnv_init()
1175 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS); in pnv_init()
1178 mc146818_rtc_init(pnv->isa_bus, 2000, NULL); in pnv_init()
1185 pnv->bmc = pnv_bmc_create(pnv->pnor); in pnv_init()
1186 pnv_ipmi_bt_init(pnv->isa_bus, pnv->bmc, 10); in pnv_init()
1194 memory_region_add_subregion(pnv->chips[0]->fw_mr, pnv->pnor->lpc_address, in pnv_init()
1195 &pnv->pnor->mmio); in pnv_init()
1201 pnv->powerdown_notifier.notify = pnv_powerdown_notify; in pnv_init()
1202 qemu_register_powerdown_notifier(&pnv->powerdown_notifier); in pnv_init()
1205 * Create/Connect any machine-specific I2C devices in pnv_init()
1207 if (pmc->i2c_init) { in pnv_init()
1208 pmc->i2c_init(pnv); in pnv_init()
1213 * 0:21 Reserved - Read as zeros
1223 *pir = (chip->chip_id << 7) | (core_id << 3) | thread_id; in pnv_get_pir_tir_p8()
1238 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, chip8->xics, &local_err); in pnv_chip_power8_intc_create()
1244 pnv_cpu->intc = obj; in pnv_chip_power8_intc_create()
1252 icp_reset(ICP(pnv_cpu->intc)); in pnv_chip_power8_intc_reset()
1259 icp_destroy(ICP(pnv_cpu->intc)); in pnv_chip_power8_intc_destroy()
1260 pnv_cpu->intc = NULL; in pnv_chip_power8_intc_destroy()
1266 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), buf); in pnv_chip_power8_intc_print_info()
1270 * 0:48 Reserved - Read as zeroes
1273 * 56 Reserved - Read as zero
1283 if (chip->big_core) { in pnv_get_pir_tir_p9()
1284 /* Big-core interleaves thread ID between small-cores */ in pnv_get_pir_tir_p9()
1290 *pir = (chip->chip_id << 8) | (core_id << 3) | thread_id; in pnv_get_pir_tir_p9()
1294 *pir = (chip->chip_id << 8) | (core_id << 2) | thread_id; in pnv_get_pir_tir_p9()
1303 * 0:48 Reserved - Read as zeroes
1306 * 56 Reserved - Read as zero
1309 * 61:63 Thread/Core Chiplet ID t0-t2
1317 if (chip->big_core) { in pnv_get_pir_tir_p10()
1318 /* Big-core interleaves thread ID between small-cores */ in pnv_get_pir_tir_p10()
1324 *pir = (chip->chip_id << 8) | (core_id << 3) | thread_id; in pnv_get_pir_tir_p10()
1328 *pir = (chip->chip_id << 8) | (core_id << 2) | thread_id; in pnv_get_pir_tir_p10()
1349 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip9->xive), in pnv_chip_power9_intc_create()
1356 pnv_cpu->intc = obj; in pnv_chip_power9_intc_create()
1363 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); in pnv_chip_power9_intc_reset()
1370 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); in pnv_chip_power9_intc_destroy()
1371 pnv_cpu->intc = NULL; in pnv_chip_power9_intc_destroy()
1377 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), buf); in pnv_chip_power9_intc_print_info()
1393 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip10->xive), in pnv_chip_power10_intc_create()
1400 pnv_cpu->intc = obj; in pnv_chip_power10_intc_create()
1407 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); in pnv_chip_power10_intc_reset()
1414 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); in pnv_chip_power10_intc_destroy()
1415 pnv_cpu->intc = NULL; in pnv_chip_power10_intc_destroy()
1421 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), buf); in pnv_chip_power10_intc_print_info()
1428 * EX1 - Venice only
1429 * EX2 - Venice only
1430 * EX3 - Venice only
1435 * EX9 - Venice only
1436 * EX10 - Venice only
1437 * EX11 - Venice only
1461 (Object **)&chip8->xics, in pnv_chip_power8_instance_init()
1465 object_initialize_child(obj, "psi", &chip8->psi, TYPE_PNV8_PSI); in pnv_chip_power8_instance_init()
1467 object_initialize_child(obj, "lpc", &chip8->lpc, TYPE_PNV8_LPC); in pnv_chip_power8_instance_init()
1469 object_initialize_child(obj, "occ", &chip8->occ, TYPE_PNV8_OCC); in pnv_chip_power8_instance_init()
1471 object_initialize_child(obj, "homer", &chip8->homer, TYPE_PNV8_HOMER); in pnv_chip_power8_instance_init()
1474 chip8->num_phbs = pcc->num_phbs; in pnv_chip_power8_instance_init()
1476 for (i = 0; i < chip8->num_phbs; i++) { in pnv_chip_power8_instance_init()
1487 chip8->phbs[i] = PNV_PHB(phb); in pnv_chip_power8_instance_init()
1500 name = g_strdup_printf("icp-%x", chip->chip_id); in pnv_chip_icp_realize()
1501 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE); in pnv_chip_icp_realize()
1504 &chip8->icp_mmio); in pnv_chip_icp_realize()
1507 for (i = 0; i < chip->nr_cores; i++) { in pnv_chip_icp_realize()
1508 PnvCore *pnv_core = chip->cores[i]; in pnv_chip_icp_realize()
1509 int core_hwid = CPU_CORE(pnv_core)->core_id; in pnv_chip_icp_realize()
1511 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { in pnv_chip_icp_realize()
1515 pcc->get_pir_tir(chip, core_hwid, j, &pir, NULL); in pnv_chip_icp_realize()
1516 icp = PNV_ICP(xics_icp_get(chip8->xics, pir)); in pnv_chip_icp_realize()
1518 memory_region_add_subregion(&chip8->icp_mmio, pir << 12, in pnv_chip_icp_realize()
1519 &icp->mmio); in pnv_chip_icp_realize()
1529 Pnv8Psi *psi8 = &chip8->psi; in pnv_chip_power8_realize()
1533 assert(chip8->xics); in pnv_chip_power8_realize()
1538 pcc->parent_realize(dev, &local_err); in pnv_chip_power8_realize()
1548 OBJECT(chip8->xics), &error_abort); in pnv_chip_power8_realize()
1553 &PNV_PSI(psi8)->xscom_regs); in pnv_chip_power8_realize()
1556 qdev_realize(DEVICE(&chip8->lpc), NULL, &error_fatal); in pnv_chip_power8_realize()
1557 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs); in pnv_chip_power8_realize()
1559 chip->fw_mr = &chip8->lpc.isa_fw; in pnv_chip_power8_realize()
1560 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x", in pnv_chip_power8_realize()
1575 object_property_set_link(OBJECT(&chip8->homer), "chip", OBJECT(chip), in pnv_chip_power8_realize()
1577 if (!qdev_realize(DEVICE(&chip8->homer), NULL, errp)) { in pnv_chip_power8_realize()
1581 pnv_xscom_add_subregion(chip, PNV_XSCOM_PBA_BASE, &chip8->homer.pba_regs); in pnv_chip_power8_realize()
1583 memory_region_add_subregion(get_system_memory(), chip8->homer.base, in pnv_chip_power8_realize()
1584 &chip8->homer.mem); in pnv_chip_power8_realize()
1587 object_property_set_link(OBJECT(&chip8->occ), "homer", in pnv_chip_power8_realize()
1588 OBJECT(&chip8->homer), &error_abort); in pnv_chip_power8_realize()
1589 if (!qdev_realize(DEVICE(&chip8->occ), NULL, errp)) { in pnv_chip_power8_realize()
1592 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs); in pnv_chip_power8_realize()
1593 qdev_connect_gpio_out(DEVICE(&chip8->occ), 0, in pnv_chip_power8_realize()
1598 &chip8->occ.sram_regs); in pnv_chip_power8_realize()
1601 for (i = 0; i < chip8->num_phbs; i++) { in pnv_chip_power8_realize()
1602 PnvPHB *phb = chip8->phbs[i]; in pnv_chip_power8_realize()
1605 object_property_set_int(OBJECT(phb), "chip-id", chip->chip_id, in pnv_chip_power8_realize()
1617 addr &= (PNV_XSCOM_SIZE - 1); in pnv_chip_power8_xscom_pcba()
1626 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */ in pnv_chip_power8e_class_init()
1627 k->cores_mask = POWER8E_CORE_MASK; in pnv_chip_power8e_class_init()
1628 k->num_phbs = 3; in pnv_chip_power8e_class_init()
1629 k->get_pir_tir = pnv_get_pir_tir_p8; in pnv_chip_power8e_class_init()
1630 k->intc_create = pnv_chip_power8_intc_create; in pnv_chip_power8e_class_init()
1631 k->intc_reset = pnv_chip_power8_intc_reset; in pnv_chip_power8e_class_init()
1632 k->intc_destroy = pnv_chip_power8_intc_destroy; in pnv_chip_power8e_class_init()
1633 k->intc_print_info = pnv_chip_power8_intc_print_info; in pnv_chip_power8e_class_init()
1634 k->isa_create = pnv_chip_power8_isa_create; in pnv_chip_power8e_class_init()
1635 k->dt_populate = pnv_chip_power8_dt_populate; in pnv_chip_power8e_class_init()
1636 k->pic_print_info = pnv_chip_power8_pic_print_info; in pnv_chip_power8e_class_init()
1637 k->xscom_core_base = pnv_chip_power8_xscom_core_base; in pnv_chip_power8e_class_init()
1638 k->xscom_pcba = pnv_chip_power8_xscom_pcba; in pnv_chip_power8e_class_init()
1639 dc->desc = "PowerNV Chip POWER8E"; in pnv_chip_power8e_class_init()
1642 &k->parent_realize); in pnv_chip_power8e_class_init()
1650 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */ in pnv_chip_power8_class_init()
1651 k->cores_mask = POWER8_CORE_MASK; in pnv_chip_power8_class_init()
1652 k->num_phbs = 3; in pnv_chip_power8_class_init()
1653 k->get_pir_tir = pnv_get_pir_tir_p8; in pnv_chip_power8_class_init()
1654 k->intc_create = pnv_chip_power8_intc_create; in pnv_chip_power8_class_init()
1655 k->intc_reset = pnv_chip_power8_intc_reset; in pnv_chip_power8_class_init()
1656 k->intc_destroy = pnv_chip_power8_intc_destroy; in pnv_chip_power8_class_init()
1657 k->intc_print_info = pnv_chip_power8_intc_print_info; in pnv_chip_power8_class_init()
1658 k->isa_create = pnv_chip_power8_isa_create; in pnv_chip_power8_class_init()
1659 k->dt_populate = pnv_chip_power8_dt_populate; in pnv_chip_power8_class_init()
1660 k->pic_print_info = pnv_chip_power8_pic_print_info; in pnv_chip_power8_class_init()
1661 k->xscom_core_base = pnv_chip_power8_xscom_core_base; in pnv_chip_power8_class_init()
1662 k->xscom_pcba = pnv_chip_power8_xscom_pcba; in pnv_chip_power8_class_init()
1663 dc->desc = "PowerNV Chip POWER8"; in pnv_chip_power8_class_init()
1666 &k->parent_realize); in pnv_chip_power8_class_init()
1674 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */ in pnv_chip_power8nvl_class_init()
1675 k->cores_mask = POWER8_CORE_MASK; in pnv_chip_power8nvl_class_init()
1676 k->num_phbs = 4; in pnv_chip_power8nvl_class_init()
1677 k->get_pir_tir = pnv_get_pir_tir_p8; in pnv_chip_power8nvl_class_init()
1678 k->intc_create = pnv_chip_power8_intc_create; in pnv_chip_power8nvl_class_init()
1679 k->intc_reset = pnv_chip_power8_intc_reset; in pnv_chip_power8nvl_class_init()
1680 k->intc_destroy = pnv_chip_power8_intc_destroy; in pnv_chip_power8nvl_class_init()
1681 k->intc_print_info = pnv_chip_power8_intc_print_info; in pnv_chip_power8nvl_class_init()
1682 k->isa_create = pnv_chip_power8nvl_isa_create; in pnv_chip_power8nvl_class_init()
1683 k->dt_populate = pnv_chip_power8_dt_populate; in pnv_chip_power8nvl_class_init()
1684 k->pic_print_info = pnv_chip_power8_pic_print_info; in pnv_chip_power8nvl_class_init()
1685 k->xscom_core_base = pnv_chip_power8_xscom_core_base; in pnv_chip_power8nvl_class_init()
1686 k->xscom_pcba = pnv_chip_power8_xscom_pcba; in pnv_chip_power8nvl_class_init()
1687 dc->desc = "PowerNV Chip POWER8NVL"; in pnv_chip_power8nvl_class_init()
1690 &k->parent_realize); in pnv_chip_power8nvl_class_init()
1700 object_initialize_child(obj, "adu", &chip9->adu, TYPE_PNV_ADU); in pnv_chip_power9_instance_init()
1701 object_initialize_child(obj, "xive", &chip9->xive, TYPE_PNV_XIVE); in pnv_chip_power9_instance_init()
1702 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip9->xive), in pnv_chip_power9_instance_init()
1703 "xive-fabric"); in pnv_chip_power9_instance_init()
1705 object_initialize_child(obj, "psi", &chip9->psi, TYPE_PNV9_PSI); in pnv_chip_power9_instance_init()
1707 object_initialize_child(obj, "lpc", &chip9->lpc, TYPE_PNV9_LPC); in pnv_chip_power9_instance_init()
1709 object_initialize_child(obj, "chiptod", &chip9->chiptod, TYPE_PNV9_CHIPTOD); in pnv_chip_power9_instance_init()
1711 object_initialize_child(obj, "occ", &chip9->occ, TYPE_PNV9_OCC); in pnv_chip_power9_instance_init()
1713 object_initialize_child(obj, "sbe", &chip9->sbe, TYPE_PNV9_SBE); in pnv_chip_power9_instance_init()
1715 object_initialize_child(obj, "homer", &chip9->homer, TYPE_PNV9_HOMER); in pnv_chip_power9_instance_init()
1718 chip->num_pecs = pcc->num_pecs; in pnv_chip_power9_instance_init()
1720 for (i = 0; i < chip->num_pecs; i++) { in pnv_chip_power9_instance_init()
1721 object_initialize_child(obj, "pec[*]", &chip9->pecs[i], in pnv_chip_power9_instance_init()
1725 for (i = 0; i < pcc->i2c_num_engines; i++) { in pnv_chip_power9_instance_init()
1726 object_initialize_child(obj, "i2c[*]", &chip9->i2c[i], TYPE_PNV_I2C); in pnv_chip_power9_instance_init()
1735 int core_id = CPU_CORE(pnv_core)->core_id; in pnv_chip_quad_realize_one()
1742 object_property_set_int(OBJECT(eq), "quad-id", core_id, &error_fatal); in pnv_chip_quad_realize_one()
1751 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); in pnv_chip_quad_realize()
1752 chip9->quads = g_new0(PnvQuad, chip9->nr_quads); in pnv_chip_quad_realize()
1754 for (i = 0; i < chip9->nr_quads; i++) { in pnv_chip_quad_realize()
1755 PnvQuad *eq = &chip9->quads[i]; in pnv_chip_quad_realize()
1757 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4], in pnv_chip_quad_realize()
1760 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->quad_id), in pnv_chip_quad_realize()
1761 &eq->xscom_regs); in pnv_chip_quad_realize()
1770 for (i = 0; i < chip->num_pecs; i++) { in pnv_chip_power9_pec_realize()
1771 PnvPhb4PecState *pec = &chip9->pecs[i]; in pnv_chip_power9_pec_realize()
1778 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id, in pnv_chip_power9_pec_realize()
1786 pec_cplt_base = pecc->xscom_cplt_base(pec); in pnv_chip_power9_pec_realize()
1787 pec_nest_base = pecc->xscom_nest_base(pec); in pnv_chip_power9_pec_realize()
1788 pec_pci_base = pecc->xscom_pci_base(pec); in pnv_chip_power9_pec_realize()
1791 &pec->nest_pervasive.xscom_ctrl_regs_mr); in pnv_chip_power9_pec_realize()
1792 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); in pnv_chip_power9_pec_realize()
1793 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); in pnv_chip_power9_pec_realize()
1802 Pnv9Psi *psi9 = &chip9->psi; in pnv_chip_power9_realize()
1809 pcc->parent_realize(dev, &local_err); in pnv_chip_power9_realize()
1816 object_property_set_link(OBJECT(&chip9->adu), "lpc", OBJECT(&chip9->lpc), in pnv_chip_power9_realize()
1818 if (!qdev_realize(DEVICE(&chip9->adu), NULL, errp)) { in pnv_chip_power9_realize()
1822 &chip9->adu.xscom_regs); in pnv_chip_power9_realize()
1831 object_property_set_int(OBJECT(&chip9->xive), "ic-bar", in pnv_chip_power9_realize()
1833 object_property_set_int(OBJECT(&chip9->xive), "vc-bar", in pnv_chip_power9_realize()
1835 object_property_set_int(OBJECT(&chip9->xive), "pc-bar", in pnv_chip_power9_realize()
1837 object_property_set_int(OBJECT(&chip9->xive), "tm-bar", in pnv_chip_power9_realize()
1839 object_property_set_link(OBJECT(&chip9->xive), "chip", OBJECT(chip), in pnv_chip_power9_realize()
1841 if (!sysbus_realize(SYS_BUS_DEVICE(&chip9->xive), errp)) { in pnv_chip_power9_realize()
1845 &chip9->xive.xscom_regs); in pnv_chip_power9_realize()
1857 &PNV_PSI(psi9)->xscom_regs); in pnv_chip_power9_realize()
1860 if (!qdev_realize(DEVICE(&chip9->lpc), NULL, errp)) { in pnv_chip_power9_realize()
1864 &chip9->lpc.xscom_regs); in pnv_chip_power9_realize()
1866 chip->fw_mr = &chip9->lpc.isa_fw; in pnv_chip_power9_realize()
1867 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", in pnv_chip_power9_realize()
1871 object_property_set_bool(OBJECT(&chip9->chiptod), "primary", in pnv_chip_power9_realize()
1872 chip->chip_id == 0, &error_abort); in pnv_chip_power9_realize()
1873 object_property_set_bool(OBJECT(&chip9->chiptod), "secondary", in pnv_chip_power9_realize()
1874 chip->chip_id == 1, &error_abort); in pnv_chip_power9_realize()
1875 object_property_set_link(OBJECT(&chip9->chiptod), "chip", OBJECT(chip), in pnv_chip_power9_realize()
1877 if (!qdev_realize(DEVICE(&chip9->chiptod), NULL, errp)) { in pnv_chip_power9_realize()
1881 &chip9->chiptod.xscom_regs); in pnv_chip_power9_realize()
1884 if (!qdev_realize(DEVICE(&chip9->sbe), NULL, errp)) { in pnv_chip_power9_realize()
1888 &chip9->sbe.xscom_ctrl_regs); in pnv_chip_power9_realize()
1890 &chip9->sbe.xscom_mbox_regs); in pnv_chip_power9_realize()
1891 qdev_connect_gpio_out(DEVICE(&chip9->sbe), 0, qdev_get_gpio_in( in pnv_chip_power9_realize()
1895 object_property_set_link(OBJECT(&chip9->homer), "chip", OBJECT(chip), in pnv_chip_power9_realize()
1897 if (!qdev_realize(DEVICE(&chip9->homer), NULL, errp)) { in pnv_chip_power9_realize()
1901 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PBA_BASE, &chip9->homer.pba_regs); in pnv_chip_power9_realize()
1903 memory_region_add_subregion(get_system_memory(), chip9->homer.base, in pnv_chip_power9_realize()
1904 &chip9->homer.mem); in pnv_chip_power9_realize()
1907 object_property_set_link(OBJECT(&chip9->occ), "homer", in pnv_chip_power9_realize()
1908 OBJECT(&chip9->homer), &error_abort); in pnv_chip_power9_realize()
1909 if (!qdev_realize(DEVICE(&chip9->occ), NULL, errp)) { in pnv_chip_power9_realize()
1912 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs); in pnv_chip_power9_realize()
1913 qdev_connect_gpio_out(DEVICE(&chip9->occ), 0, qdev_get_gpio_in( in pnv_chip_power9_realize()
1918 &chip9->occ.sram_regs); in pnv_chip_power9_realize()
1930 for (i = 0; i < pcc->i2c_num_engines; i++) { in pnv_chip_power9_realize()
1931 Object *obj = OBJECT(&chip9->i2c[i]); in pnv_chip_power9_realize()
1934 object_property_set_int(obj, "num-busses", in pnv_chip_power9_realize()
1935 pcc->i2c_ports_per_engine[i], in pnv_chip_power9_realize()
1942 (chip9->i2c[i].engine - 1) * in pnv_chip_power9_realize()
1944 &chip9->i2c[i].xscom_regs); in pnv_chip_power9_realize()
1945 qdev_connect_gpio_out(DEVICE(&chip9->i2c[i]), 0, in pnv_chip_power9_realize()
1953 addr &= (PNV9_XSCOM_SIZE - 1); in pnv_chip_power9_xscom_pcba()
1963 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */ in pnv_chip_power9_class_init()
1964 k->cores_mask = POWER9_CORE_MASK; in pnv_chip_power9_class_init()
1965 k->get_pir_tir = pnv_get_pir_tir_p9; in pnv_chip_power9_class_init()
1966 k->intc_create = pnv_chip_power9_intc_create; in pnv_chip_power9_class_init()
1967 k->intc_reset = pnv_chip_power9_intc_reset; in pnv_chip_power9_class_init()
1968 k->intc_destroy = pnv_chip_power9_intc_destroy; in pnv_chip_power9_class_init()
1969 k->intc_print_info = pnv_chip_power9_intc_print_info; in pnv_chip_power9_class_init()
1970 k->isa_create = pnv_chip_power9_isa_create; in pnv_chip_power9_class_init()
1971 k->dt_populate = pnv_chip_power9_dt_populate; in pnv_chip_power9_class_init()
1972 k->pic_print_info = pnv_chip_power9_pic_print_info; in pnv_chip_power9_class_init()
1973 k->xscom_core_base = pnv_chip_power9_xscom_core_base; in pnv_chip_power9_class_init()
1974 k->xscom_pcba = pnv_chip_power9_xscom_pcba; in pnv_chip_power9_class_init()
1975 dc->desc = "PowerNV Chip POWER9"; in pnv_chip_power9_class_init()
1976 k->num_pecs = PNV9_CHIP_MAX_PEC; in pnv_chip_power9_class_init()
1977 k->i2c_num_engines = PNV9_CHIP_MAX_I2C; in pnv_chip_power9_class_init()
1978 k->i2c_ports_per_engine = i2c_ports_per_engine; in pnv_chip_power9_class_init()
1981 &k->parent_realize); in pnv_chip_power9_class_init()
1991 object_initialize_child(obj, "adu", &chip10->adu, TYPE_PNV_ADU); in pnv_chip_power10_instance_init()
1992 object_initialize_child(obj, "xive", &chip10->xive, TYPE_PNV_XIVE2); in pnv_chip_power10_instance_init()
1993 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip10->xive), in pnv_chip_power10_instance_init()
1994 "xive-fabric"); in pnv_chip_power10_instance_init()
1995 object_initialize_child(obj, "psi", &chip10->psi, TYPE_PNV10_PSI); in pnv_chip_power10_instance_init()
1996 object_initialize_child(obj, "lpc", &chip10->lpc, TYPE_PNV10_LPC); in pnv_chip_power10_instance_init()
1997 object_initialize_child(obj, "chiptod", &chip10->chiptod, in pnv_chip_power10_instance_init()
1999 object_initialize_child(obj, "occ", &chip10->occ, TYPE_PNV10_OCC); in pnv_chip_power10_instance_init()
2000 object_initialize_child(obj, "sbe", &chip10->sbe, TYPE_PNV10_SBE); in pnv_chip_power10_instance_init()
2001 object_initialize_child(obj, "homer", &chip10->homer, TYPE_PNV10_HOMER); in pnv_chip_power10_instance_init()
2002 object_initialize_child(obj, "n1-chiplet", &chip10->n1_chiplet, in pnv_chip_power10_instance_init()
2005 chip->num_pecs = pcc->num_pecs; in pnv_chip_power10_instance_init()
2007 for (i = 0; i < chip->num_pecs; i++) { in pnv_chip_power10_instance_init()
2008 object_initialize_child(obj, "pec[*]", &chip10->pecs[i], in pnv_chip_power10_instance_init()
2012 for (i = 0; i < pcc->i2c_num_engines; i++) { in pnv_chip_power10_instance_init()
2013 object_initialize_child(obj, "i2c[*]", &chip10->i2c[i], TYPE_PNV_I2C); in pnv_chip_power10_instance_init()
2017 object_initialize_child(obj, "pib_spic[*]", &chip10->pib_spic[i], in pnv_chip_power10_instance_init()
2027 chip10->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); in pnv_chip_power10_quad_realize()
2028 chip10->quads = g_new0(PnvQuad, chip10->nr_quads); in pnv_chip_power10_quad_realize()
2030 for (i = 0; i < chip10->nr_quads; i++) { in pnv_chip_power10_quad_realize()
2031 PnvQuad *eq = &chip10->quads[i]; in pnv_chip_power10_quad_realize()
2033 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4], in pnv_chip_power10_quad_realize()
2036 pnv_xscom_add_subregion(chip, PNV10_XSCOM_EQ_BASE(eq->quad_id), in pnv_chip_power10_quad_realize()
2037 &eq->xscom_regs); in pnv_chip_power10_quad_realize()
2039 pnv_xscom_add_subregion(chip, PNV10_XSCOM_QME_BASE(eq->quad_id), in pnv_chip_power10_quad_realize()
2040 &eq->xscom_qme_regs); in pnv_chip_power10_quad_realize()
2049 for (i = 0; i < chip->num_pecs; i++) { in pnv_chip_power10_phb_realize()
2050 PnvPhb4PecState *pec = &chip10->pecs[i]; in pnv_chip_power10_phb_realize()
2057 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id, in pnv_chip_power10_phb_realize()
2065 pec_cplt_base = pecc->xscom_cplt_base(pec); in pnv_chip_power10_phb_realize()
2066 pec_nest_base = pecc->xscom_nest_base(pec); in pnv_chip_power10_phb_realize()
2067 pec_pci_base = pecc->xscom_pci_base(pec); in pnv_chip_power10_phb_realize()
2070 &pec->nest_pervasive.xscom_ctrl_regs_mr); in pnv_chip_power10_phb_realize()
2071 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); in pnv_chip_power10_phb_realize()
2072 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); in pnv_chip_power10_phb_realize()
2087 pcc->parent_realize(dev, &local_err); in pnv_chip_power10_realize()
2094 object_property_set_link(OBJECT(&chip10->adu), "lpc", OBJECT(&chip10->lpc), in pnv_chip_power10_realize()
2096 if (!qdev_realize(DEVICE(&chip10->adu), NULL, errp)) { in pnv_chip_power10_realize()
2100 &chip10->adu.xscom_regs); in pnv_chip_power10_realize()
2109 object_property_set_int(OBJECT(&chip10->xive), "ic-bar", in pnv_chip_power10_realize()
2111 object_property_set_int(OBJECT(&chip10->xive), "esb-bar", in pnv_chip_power10_realize()
2113 object_property_set_int(OBJECT(&chip10->xive), "end-bar", in pnv_chip_power10_realize()
2115 object_property_set_int(OBJECT(&chip10->xive), "nvpg-bar", in pnv_chip_power10_realize()
2117 object_property_set_int(OBJECT(&chip10->xive), "nvc-bar", in pnv_chip_power10_realize()
2119 object_property_set_int(OBJECT(&chip10->xive), "tm-bar", in pnv_chip_power10_realize()
2121 object_property_set_link(OBJECT(&chip10->xive), "chip", OBJECT(chip), in pnv_chip_power10_realize()
2123 if (!sysbus_realize(SYS_BUS_DEVICE(&chip10->xive), errp)) { in pnv_chip_power10_realize()
2127 &chip10->xive.xscom_regs); in pnv_chip_power10_realize()
2130 object_property_set_int(OBJECT(&chip10->psi), "bar", in pnv_chip_power10_realize()
2133 object_property_set_int(OBJECT(&chip10->psi), "shift", XIVE_ESB_64K, in pnv_chip_power10_realize()
2135 if (!qdev_realize(DEVICE(&chip10->psi), NULL, errp)) { in pnv_chip_power10_realize()
2139 &PNV_PSI(&chip10->psi)->xscom_regs); in pnv_chip_power10_realize()
2142 if (!qdev_realize(DEVICE(&chip10->lpc), NULL, errp)) { in pnv_chip_power10_realize()
2146 &chip10->lpc.xscom_regs); in pnv_chip_power10_realize()
2148 chip->fw_mr = &chip10->lpc.isa_fw; in pnv_chip_power10_realize()
2149 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", in pnv_chip_power10_realize()
2153 object_property_set_bool(OBJECT(&chip10->chiptod), "primary", in pnv_chip_power10_realize()
2154 chip->chip_id == 0, &error_abort); in pnv_chip_power10_realize()
2155 object_property_set_bool(OBJECT(&chip10->chiptod), "secondary", in pnv_chip_power10_realize()
2156 chip->chip_id == 1, &error_abort); in pnv_chip_power10_realize()
2157 object_property_set_link(OBJECT(&chip10->chiptod), "chip", OBJECT(chip), in pnv_chip_power10_realize()
2159 if (!qdev_realize(DEVICE(&chip10->chiptod), NULL, errp)) { in pnv_chip_power10_realize()
2163 &chip10->chiptod.xscom_regs); in pnv_chip_power10_realize()
2166 object_property_set_link(OBJECT(&chip10->homer), "chip", OBJECT(chip), in pnv_chip_power10_realize()
2168 if (!qdev_realize(DEVICE(&chip10->homer), NULL, errp)) { in pnv_chip_power10_realize()
2173 &chip10->homer.pba_regs); in pnv_chip_power10_realize()
2175 memory_region_add_subregion(get_system_memory(), chip10->homer.base, in pnv_chip_power10_realize()
2176 &chip10->homer.mem); in pnv_chip_power10_realize()
2179 object_property_set_link(OBJECT(&chip10->occ), "homer", in pnv_chip_power10_realize()
2180 OBJECT(&chip10->homer), &error_abort); in pnv_chip_power10_realize()
2181 if (!qdev_realize(DEVICE(&chip10->occ), NULL, errp)) { in pnv_chip_power10_realize()
2185 &chip10->occ.xscom_regs); in pnv_chip_power10_realize()
2186 qdev_connect_gpio_out(DEVICE(&chip10->occ), 0, qdev_get_gpio_in( in pnv_chip_power10_realize()
2187 DEVICE(&chip10->psi), PSIHB9_IRQ_OCC)); in pnv_chip_power10_realize()
2192 &chip10->occ.sram_regs); in pnv_chip_power10_realize()
2195 if (!qdev_realize(DEVICE(&chip10->sbe), NULL, errp)) { in pnv_chip_power10_realize()
2199 &chip10->sbe.xscom_ctrl_regs); in pnv_chip_power10_realize()
2201 &chip10->sbe.xscom_mbox_regs); in pnv_chip_power10_realize()
2202 qdev_connect_gpio_out(DEVICE(&chip10->sbe), 0, qdev_get_gpio_in( in pnv_chip_power10_realize()
2203 DEVICE(&chip10->psi), PSIHB9_IRQ_PSU)); in pnv_chip_power10_realize()
2206 if (!qdev_realize(DEVICE(&chip10->n1_chiplet), NULL, errp)) { in pnv_chip_power10_realize()
2210 &chip10->n1_chiplet.nest_pervasive.xscom_ctrl_regs_mr); in pnv_chip_power10_realize()
2213 &chip10->n1_chiplet.xscom_pb_eq_mr); in pnv_chip_power10_realize()
2216 &chip10->n1_chiplet.xscom_pb_es_mr); in pnv_chip_power10_realize()
2229 for (i = 0; i < pcc->i2c_num_engines; i++) { in pnv_chip_power10_realize()
2230 Object *obj = OBJECT(&chip10->i2c[i]); in pnv_chip_power10_realize()
2233 object_property_set_int(obj, "num-busses", in pnv_chip_power10_realize()
2234 pcc->i2c_ports_per_engine[i], in pnv_chip_power10_realize()
2241 (chip10->i2c[i].engine - 1) * in pnv_chip_power10_realize()
2243 &chip10->i2c[i].xscom_regs); in pnv_chip_power10_realize()
2244 qdev_connect_gpio_out(DEVICE(&chip10->i2c[i]), 0, in pnv_chip_power10_realize()
2245 qdev_get_gpio_in(DEVICE(&chip10->psi), in pnv_chip_power10_realize()
2250 object_property_set_int(OBJECT(&chip10->pib_spic[i]), "spic_num", in pnv_chip_power10_realize()
2253 object_property_set_int(OBJECT(&chip10->pib_spic[i]), "transfer_len", in pnv_chip_power10_realize()
2255 object_property_set_int(OBJECT(&chip10->pib_spic[i]), "chip-id", in pnv_chip_power10_realize()
2256 chip->chip_id, &error_fatal); in pnv_chip_power10_realize()
2258 (&chip10->pib_spic[i])), errp)) { in pnv_chip_power10_realize()
2263 &chip10->pib_spic[i].xscom_spic_regs); in pnv_chip_power10_realize()
2270 for (i = 0; i < pnv->num_chips; i++) { in pnv_rainier_i2c_init()
2271 Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]); in pnv_rainier_i2c_init()
2277 I2CSlave *dev = i2c_slave_create_simple(chip10->i2c[2].busses[1], in pnv_rainier_i2c_init()
2281 * Connect PCA9552 GPIO pins 0-4 (SLOTx_EN) outputs to GPIO pins 5-9 in pnv_rainier_i2c_init()
2295 i2c_slave_create_simple(chip10->i2c[2].busses[1], "pca9554", 0x25); in pnv_rainier_i2c_init()
2301 addr &= (PNV10_XSCOM_SIZE - 1); in pnv_chip_power10_xscom_pcba()
2311 k->chip_cfam_id = 0x220da04980000000ull; /* P10 DD2.0 (with NX) */ in pnv_chip_power10_class_init()
2312 k->cores_mask = POWER10_CORE_MASK; in pnv_chip_power10_class_init()
2313 k->get_pir_tir = pnv_get_pir_tir_p10; in pnv_chip_power10_class_init()
2314 k->intc_create = pnv_chip_power10_intc_create; in pnv_chip_power10_class_init()
2315 k->intc_reset = pnv_chip_power10_intc_reset; in pnv_chip_power10_class_init()
2316 k->intc_destroy = pnv_chip_power10_intc_destroy; in pnv_chip_power10_class_init()
2317 k->intc_print_info = pnv_chip_power10_intc_print_info; in pnv_chip_power10_class_init()
2318 k->isa_create = pnv_chip_power10_isa_create; in pnv_chip_power10_class_init()
2319 k->dt_populate = pnv_chip_power10_dt_populate; in pnv_chip_power10_class_init()
2320 k->pic_print_info = pnv_chip_power10_pic_print_info; in pnv_chip_power10_class_init()
2321 k->xscom_core_base = pnv_chip_power10_xscom_core_base; in pnv_chip_power10_class_init()
2322 k->xscom_pcba = pnv_chip_power10_xscom_pcba; in pnv_chip_power10_class_init()
2323 dc->desc = "PowerNV Chip POWER10"; in pnv_chip_power10_class_init()
2324 k->num_pecs = PNV10_CHIP_MAX_PEC; in pnv_chip_power10_class_init()
2325 k->i2c_num_engines = PNV10_CHIP_MAX_I2C; in pnv_chip_power10_class_init()
2326 k->i2c_ports_per_engine = i2c_ports_per_engine; in pnv_chip_power10_class_init()
2329 &k->parent_realize); in pnv_chip_power10_class_init()
2342 if (!chip->cores_mask) { in pnv_chip_core_sanitize()
2343 chip->cores_mask = pcc->cores_mask; in pnv_chip_core_sanitize()
2347 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) { in pnv_chip_core_sanitize()
2349 chip->cores_mask); in pnv_chip_core_sanitize()
2352 chip->cores_mask &= pcc->cores_mask; in pnv_chip_core_sanitize()
2354 /* Ensure small-cores a paired up in big-core mode */ in pnv_chip_core_sanitize()
2355 if (pnv->big_core) { in pnv_chip_core_sanitize()
2356 uint64_t even_cores = chip->cores_mask & 0x5555555555555555ULL; in pnv_chip_core_sanitize()
2357 uint64_t odd_cores = chip->cores_mask & 0xaaaaaaaaaaaaaaaaULL; in pnv_chip_core_sanitize()
2360 error_setg(errp, "warning: unpaired cores in big-core mode !"); in pnv_chip_core_sanitize()
2366 cores_max = ctpop64(chip->cores_mask); in pnv_chip_core_sanitize()
2367 if (chip->nr_cores > cores_max) { in pnv_chip_core_sanitize()
2395 chip->cores = g_new0(PnvCore *, chip->nr_cores); in pnv_chip_core_realize()
2397 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8) in pnv_chip_core_realize()
2398 && (i < chip->nr_cores); core_hwid++) { in pnv_chip_core_realize()
2403 if (!(chip->cores_mask & (1ull << core_hwid))) { in pnv_chip_core_realize()
2411 chip->cores[i] = pnv_core; in pnv_chip_core_realize()
2412 object_property_set_int(OBJECT(pnv_core), "nr-threads", in pnv_chip_core_realize()
2413 chip->nr_threads, &error_fatal); in pnv_chip_core_realize()
2418 object_property_set_int(OBJECT(pnv_core), "hrmor", pnv->fw_load_addr, in pnv_chip_core_realize()
2420 object_property_set_bool(OBJECT(pnv_core), "big-core", chip->big_core, in pnv_chip_core_realize()
2422 object_property_set_bool(OBJECT(pnv_core), "quirk-tb-big-core", in pnv_chip_core_realize()
2423 pmc->quirk_tb_big_core, &error_fatal); in pnv_chip_core_realize()
2424 object_property_set_bool(OBJECT(pnv_core), "lpar-per-core", in pnv_chip_core_realize()
2425 chip->lpar_per_core, &error_fatal); in pnv_chip_core_realize()
2432 xscom_core_base = pcc->xscom_core_base(chip, core_hwid); in pnv_chip_core_realize()
2435 &pnv_core->xscom_regs); in pnv_chip_core_realize()
2454 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0),
2455 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0),
2456 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0),
2457 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1),
2458 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0),
2459 DEFINE_PROP_UINT32("nr-threads", PnvChip, nr_threads, 1),
2460 DEFINE_PROP_BOOL("big-core", PnvChip, big_core, false),
2461 DEFINE_PROP_BOOL("lpar-per-core", PnvChip, lpar_per_core, false),
2468 set_bit(DEVICE_CATEGORY_CPU, dc->categories); in pnv_chip_class_init()
2469 dc->realize = pnv_chip_realize; in pnv_chip_class_init()
2471 dc->desc = "PowerNV Chip"; in pnv_chip_class_init()
2478 for (i = 0; i < chip->nr_cores; i++) { in pnv_chip_find_core()
2479 PnvCore *pc = chip->cores[i]; in pnv_chip_find_core()
2482 if (cc->core_id == core_id) { in pnv_chip_find_core()
2493 for (i = 0; i < chip->nr_cores; i++) { in pnv_chip_find_cpu()
2494 PnvCore *pc = chip->cores[i]; in pnv_chip_find_cpu()
2497 for (j = 0; j < cc->nr_threads; j++) { in pnv_chip_find_cpu()
2498 if (ppc_cpu_pir(pc->threads[j]) == pir) { in pnv_chip_find_cpu()
2499 return pc->threads[j]; in pnv_chip_find_cpu()
2512 for (i = 0; i < chip->nr_cores; i++) { in pnv_chip_foreach_cpu()
2513 PnvCore *pc = chip->cores[i]; in pnv_chip_foreach_cpu()
2515 for (j = 0; j < CPU_CORE(pc)->nr_threads; j++) { in pnv_chip_foreach_cpu()
2516 fn(chip, pc->threads[j], opaque); in pnv_chip_foreach_cpu()
2526 for (i = 0; i < pnv->num_chips; i++) { in pnv_ics_get()
2527 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); in pnv_ics_get()
2529 if (ics_valid_irq(&chip8->psi.ics, irq)) { in pnv_ics_get()
2530 return &chip8->psi.ics; in pnv_ics_get()
2533 for (j = 0; j < chip8->num_phbs; j++) { in pnv_ics_get()
2534 PnvPHB *phb = chip8->phbs[j]; in pnv_ics_get()
2535 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); in pnv_ics_get()
2537 if (ics_valid_irq(&phb3->lsis, irq)) { in pnv_ics_get()
2538 return &phb3->lsis; in pnv_ics_get()
2541 if (ics_valid_irq(ICS(&phb3->msis), irq)) { in pnv_ics_get()
2542 return ICS(&phb3->msis); in pnv_ics_get()
2553 for (i = 0; i < pnv->num_chips; i++) { in pnv_get_chip()
2554 PnvChip *chip = pnv->chips[i]; in pnv_get_chip()
2555 if (chip->chip_id == chip_id) { in pnv_get_chip()
2567 for (i = 0; i < pnv->num_chips; i++) { in pnv_ics_resend()
2568 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); in pnv_ics_resend()
2570 ics_resend(&chip8->psi.ics); in pnv_ics_resend()
2572 for (j = 0; j < chip8->num_phbs; j++) { in pnv_ics_resend()
2573 PnvPHB *phb = chip8->phbs[j]; in pnv_ics_resend()
2574 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); in pnv_ics_resend()
2576 ics_resend(&phb3->lsis); in pnv_ics_resend()
2577 ics_resend(ICS(&phb3->msis)); in pnv_ics_resend()
2586 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL; in pnv_icp_get()
2592 PNV_CHIP_GET_CLASS(chip)->intc_print_info(chip, cpu, opaque); in pnv_pic_intc_print_info()
2600 for (i = 0; i < pnv->num_chips; i++) { in pnv_pic_print_info()
2601 PnvChip *chip = pnv->chips[i]; in pnv_pic_print_info()
2607 PNV_CHIP_GET_CLASS(chip)->pic_print_info(chip, buf); in pnv_pic_print_info()
2621 for (i = 0; i < pnv->num_chips; i++) { in pnv_match_nvt()
2622 Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]); in pnv_match_nvt()
2623 XivePresenter *xptr = XIVE_PRESENTER(&chip9->xive); in pnv_match_nvt()
2627 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, crowd, in pnv_match_nvt()
2650 for (i = 0; i < pnv->num_chips; i++) { in pnv10_xive_match_nvt()
2651 Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]); in pnv10_xive_match_nvt()
2652 XivePresenter *xptr = XIVE_PRESENTER(&chip10->xive); in pnv10_xive_match_nvt()
2656 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, crowd, in pnv10_xive_match_nvt()
2677 for (i = 0; i < pnv->num_chips; i++) { in pnv10_xive_broadcast()
2678 Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]); in pnv10_xive_broadcast()
2679 XivePresenter *xptr = XIVE_PRESENTER(&chip10->xive); in pnv10_xive_broadcast()
2682 xpc->broadcast(xptr, nvt_blk, nvt_idx, crowd, cam_ignore, priority); in pnv10_xive_broadcast()
2690 return pnv->big_core; in pnv_machine_get_big_core()
2696 pnv->big_core = value; in pnv_machine_set_big_core()
2702 return pnv->lpar_per_core; in pnv_machine_get_lpar_per_core()
2708 pnv->lpar_per_core = value; in pnv_machine_set_lpar_per_core()
2715 return !!pnv->fw_load_addr; in pnv_machine_get_hb()
2723 pnv->fw_load_addr = 0x8000000; in pnv_machine_set_hb()
2739 mc->desc = "IBM PowerNV (Non-Virtualized) POWER8"; in pnv_machine_power8_class_init()
2740 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); in pnv_machine_power8_class_init()
2741 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); in pnv_machine_power8_class_init()
2743 xic->icp_get = pnv_icp_get; in pnv_machine_power8_class_init()
2744 xic->ics_get = pnv_ics_get; in pnv_machine_power8_class_init()
2745 xic->ics_resend = pnv_ics_resend; in pnv_machine_power8_class_init()
2747 pmc->compat = compat; in pnv_machine_power8_class_init()
2748 pmc->compat_size = sizeof(compat); in pnv_machine_power8_class_init()
2749 pmc->max_smt_threads = 8; in pnv_machine_power8_class_init()
2750 /* POWER8 is always lpar-per-core mode */ in pnv_machine_power8_class_init()
2751 pmc->has_lpar_per_thread = false; in pnv_machine_power8_class_init()
2768 mc->desc = "IBM PowerNV (Non-Virtualized) POWER9"; in pnv_machine_power9_class_init()
2769 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.2"); in pnv_machine_power9_class_init()
2770 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); in pnv_machine_power9_class_init()
2772 xfc->match_nvt = pnv_match_nvt; in pnv_machine_power9_class_init()
2774 pmc->compat = compat; in pnv_machine_power9_class_init()
2775 pmc->compat_size = sizeof(compat); in pnv_machine_power9_class_init()
2776 pmc->max_smt_threads = 4; in pnv_machine_power9_class_init()
2777 pmc->has_lpar_per_thread = true; in pnv_machine_power9_class_init()
2778 pmc->dt_power_mgt = pnv_dt_power_mgt; in pnv_machine_power9_class_init()
2782 object_class_property_add_bool(oc, "big-core", in pnv_machine_power9_class_init()
2785 object_class_property_set_description(oc, "big-core", in pnv_machine_power9_class_init()
2786 "Use big-core (aka fused-core) mode"); in pnv_machine_power9_class_init()
2788 object_class_property_add_bool(oc, "lpar-per-core", in pnv_machine_power9_class_init()
2791 object_class_property_set_description(oc, "lpar-per-core", in pnv_machine_power9_class_init()
2807 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v2.0"); in pnv_machine_p10_common_class_init()
2808 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); in pnv_machine_p10_common_class_init()
2810 mc->alias = "powernv"; in pnv_machine_p10_common_class_init()
2812 pmc->compat = compat; in pnv_machine_p10_common_class_init()
2813 pmc->compat_size = sizeof(compat); in pnv_machine_p10_common_class_init()
2814 pmc->max_smt_threads = 4; in pnv_machine_p10_common_class_init()
2815 pmc->has_lpar_per_thread = true; in pnv_machine_p10_common_class_init()
2816 pmc->quirk_tb_big_core = true; in pnv_machine_p10_common_class_init()
2817 pmc->dt_power_mgt = pnv_dt_power_mgt; in pnv_machine_p10_common_class_init()
2819 xfc->match_nvt = pnv10_xive_match_nvt; in pnv_machine_p10_common_class_init()
2820 xfc->broadcast = pnv10_xive_broadcast; in pnv_machine_p10_common_class_init()
2830 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10"; in pnv_machine_power10_class_init()
2837 object_class_property_add_bool(oc, "big-core", in pnv_machine_power10_class_init()
2840 object_class_property_set_description(oc, "big-core", in pnv_machine_power10_class_init()
2841 "Use big-core (aka fused-core) mode"); in pnv_machine_power10_class_init()
2843 object_class_property_add_bool(oc, "lpar-per-core", in pnv_machine_power10_class_init()
2846 object_class_property_set_description(oc, "lpar-per-core", in pnv_machine_power10_class_init()
2857 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10 Rainier"; in pnv_machine_p10_rainier_class_init()
2858 pmc->i2c_init = pnv_rainier_i2c_init; in pnv_machine_p10_rainier_class_init()
2867 if (env->spr[SPR_SRR1] & SRR1_WAKESTATE) { in pnv_cpu_do_nmi_on_cpu()
2869 * Power-save wakeups, as indicated by non-zero SRR1[46:47] put the in pnv_cpu_do_nmi_on_cpu()
2873 if (!(env->spr[SPR_SRR1] & SRR1_WAKERESET)) { in pnv_cpu_do_nmi_on_cpu()
2875 env->spr[SPR_SRR1] |= SRR1_WAKERESET; in pnv_cpu_do_nmi_on_cpu()
2879 * For non-powersave system resets, SRR1[42:45] are defined to be in pnv_cpu_do_nmi_on_cpu()
2880 * implementation-dependent. The POWER9 User Manual specifies that in pnv_cpu_do_nmi_on_cpu()
2885 env->spr[SPR_SRR1] |= SRR1_WAKESCOM; in pnv_cpu_do_nmi_on_cpu()
2911 for (i = 0; i < pnv->num_chips; i++) { in pnv_nmi()
2912 pnv_chip_foreach_cpu(pnv->chips[i], pnv_cpu_do_nmi, NULL); in pnv_nmi()
2922 mc->desc = "IBM PowerNV (Non-Virtualized)"; in pnv_machine_class_init()
2923 mc->init = pnv_init; in pnv_machine_class_init()
2924 mc->reset = pnv_reset; in pnv_machine_class_init()
2925 mc->max_cpus = MAX_CPUS; in pnv_machine_class_init()
2927 mc->block_default_type = IF_IDE; in pnv_machine_class_init()
2928 mc->no_parallel = 1; in pnv_machine_class_init()
2929 mc->default_boot_order = NULL; in pnv_machine_class_init()
2931 * RAM defaults to less than 2048 for 32-bit hosts, and large in pnv_machine_class_init()
2934 mc->default_ram_size = 1 * GiB; in pnv_machine_class_init()
2935 mc->default_ram_id = "pnv.ram"; in pnv_machine_class_init()
2936 ispc->print_info = pnv_pic_print_info; in pnv_machine_class_init()
2937 nc->nmi_monitor_handler = pnv_nmi; in pnv_machine_class_init()
2939 object_class_property_add_bool(oc, "hb-mode", in pnv_machine_class_init()
2941 object_class_property_set_description(oc, "hb-mode", in pnv_machine_class_init()
2968 .name = MACHINE_TYPE_NAME("powernv10-rainier"),