324     const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms);  in platform_bus_create_devtree()  local
325     gchar *node = g_strdup_printf("/platform@%"PRIx64, pmc->platform_bus_base);  in platform_bus_create_devtree()
327     uint64_t addr = pmc->platform_bus_base;  in platform_bus_create_devtree()
328     uint64_t size = pmc->platform_bus_size;  in platform_bus_create_devtree()
329     int irq_start = pmc->platform_bus_first_irq;  in platform_bus_create_devtree()
378     const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms);  in ppce500_load_device_tree()  local
400             0x2000000, 0x0, pmc->pci_mmio_bus_base,  in ppce500_load_device_tree()
401             pmc->pci_mmio_base >> 32, pmc->pci_mmio_base,  in ppce500_load_device_tree()
405             pmc->pci_pio_base >> 32, pmc->pci_pio_base,  in ppce500_load_device_tree()
499         uint64_t cpu_release_addr = pmc->spin_base + (i * 0x20);  in ppce500_load_device_tree()
534     soc = g_strdup_printf("/soc@%"PRIx64, pmc->ccsrbar_base);  in ppce500_load_device_tree()
542                            pmc->ccsrbar_base >> 32, pmc->ccsrbar_base,  in ppce500_load_device_tree()
581     if (pmc->has_esdhc) {  in ppce500_load_device_tree()
614                           pmc->ccsrbar_base + MPC8544_PCI_REGS_OFFSET);  in ppce500_load_device_tree()
622                              pmc->pci_first_slot, pmc->pci_nr_slots,  in ppce500_load_device_tree()
634                            (pmc->ccsrbar_base + MPC8544_PCI_REGS_OFFSET) >> 32,  in ppce500_load_device_tree()
635                            (pmc->ccsrbar_base + MPC8544_PCI_REGS_OFFSET),  in ppce500_load_device_tree()
644     if (pmc->has_mpc8xxx_gpio) {  in ppce500_load_device_tree()
653     pmc->fixup_devtree(fdt);  in ppce500_load_device_tree()
813     const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms);  in ppce500_init_mpic_qemu()  local
817     qdev_prop_set_uint32(dev, "model", pmc->mpic_version);  in ppce500_init_mpic_qemu()
833 static DeviceState *ppce500_init_mpic_kvm(const PPCE500MachineClass *pmc,  in ppce500_init_mpic_kvm()  argument
841     qdev_prop_set_uint32(dev, "model", pmc->mpic_version);  in ppce500_init_mpic_kvm()
866     const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms);  in ppce500_init_mpic()  local
874             dev = ppce500_init_mpic_kvm(pmc, &err);  in ppce500_init_mpic()
905     const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(machine);  in ppce500_init()  local
906     MachineClass *mc = MACHINE_CLASS(pmc);  in ppce500_init()
969         env->mpic_iack = pmc->ccsrbar_base + MPC8544_MPIC_REGS_OFFSET + 0xa0;  in ppce500_init()
1000     memory_region_add_subregion(address_space_mem, pmc->ccsrbar_base,  in ppce500_init()
1030     if (pmc->has_esdhc) {  in ppce500_init()
1065     qdev_prop_set_uint32(dev, "first_slot", pmc->pci_first_slot);  in ppce500_init()
1086     sysbus_create_simple("e500-spin", pmc->spin_base, NULL);  in ppce500_init()
1088     if (pmc->has_mpc8xxx_gpio) {  in ppce500_init()
1106     qdev_prop_set_uint32(dev, "num_irqs", pmc->platform_bus_num_irqs);  in ppce500_init()
1107     qdev_prop_set_uint32(dev, "mmio_size", pmc->platform_bus_size);  in ppce500_init()
1112     for (i = 0; i < pmc->platform_bus_num_irqs; i++) {  in ppce500_init()
1113         int irqn = pmc->platform_bus_first_irq + i;  in ppce500_init()
1118                                 pmc->platform_bus_base,  in ppce500_init()