Lines Matching +full:- +full:- +full:enable +full:- +full:fdt
2 * QEMU PowerPC e500-based platforms
20 #include "qemu/guest-random.h"
24 #include "e500-ccsr.h"
26 #include "qemu/config-file.h"
28 #include "hw/char/serial-mm.h"
30 #include "system/block-backend-io.h"
40 #include "hw/qdev-properties.h"
44 #include "qemu/host-utils.h"
46 #include "hw/pci-host/ppce500.h"
47 #include "qemu/error-report.h"
48 #include "hw/platform-bus.h"
89 static uint32_t *pci_map_create(void *fdt, uint32_t mpic, int first_slot, in pci_map_create() argument
120 static void dt_serial_create(void *fdt, unsigned long long offset, in dt_serial_create() argument
127 qemu_fdt_add_subnode(fdt, ser); in dt_serial_create()
128 qemu_fdt_setprop_string(fdt, ser, "device_type", "serial"); in dt_serial_create()
129 qemu_fdt_setprop_string(fdt, ser, "compatible", "ns16550"); in dt_serial_create()
130 qemu_fdt_setprop_cells(fdt, ser, "reg", offset, 0x100); in dt_serial_create()
131 qemu_fdt_setprop_cell(fdt, ser, "cell-index", idx); in dt_serial_create()
132 qemu_fdt_setprop_cell(fdt, ser, "clock-frequency", freq); in dt_serial_create()
133 qemu_fdt_setprop_cells(fdt, ser, "interrupts", 42, 2); in dt_serial_create()
134 qemu_fdt_setprop_phandle(fdt, ser, "interrupt-parent", mpic); in dt_serial_create()
135 qemu_fdt_setprop_string(fdt, "/aliases", alias, ser); in dt_serial_create()
139 * "linux,stdout-path" and "stdout" properties are deprecated by linux in dt_serial_create()
140 * kernel. New platforms should only use the "stdout-path" property. Set in dt_serial_create()
144 qemu_fdt_setprop_string(fdt, "/chosen", "linux,stdout-path", ser); in dt_serial_create()
145 qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", ser); in dt_serial_create()
150 static void create_dt_mpc8xxx_gpio(void *fdt, const char *soc, const char *mpic) in create_dt_mpc8xxx_gpio() argument
155 gchar *poweroff = g_strdup_printf("%s/power-off", soc); in create_dt_mpc8xxx_gpio()
158 qemu_fdt_add_subnode(fdt, node); in create_dt_mpc8xxx_gpio()
159 qemu_fdt_setprop_string(fdt, node, "compatible", "fsl,qoriq-gpio"); in create_dt_mpc8xxx_gpio()
160 qemu_fdt_setprop_cells(fdt, node, "reg", mmio0, 0x1000); in create_dt_mpc8xxx_gpio()
161 qemu_fdt_setprop_cells(fdt, node, "interrupts", irq0, 0x2); in create_dt_mpc8xxx_gpio()
162 qemu_fdt_setprop_phandle(fdt, node, "interrupt-parent", mpic); in create_dt_mpc8xxx_gpio()
163 qemu_fdt_setprop_cells(fdt, node, "#gpio-cells", 2); in create_dt_mpc8xxx_gpio()
164 qemu_fdt_setprop(fdt, node, "gpio-controller", NULL, 0); in create_dt_mpc8xxx_gpio()
165 gpio_ph = qemu_fdt_alloc_phandle(fdt); in create_dt_mpc8xxx_gpio()
166 qemu_fdt_setprop_cell(fdt, node, "phandle", gpio_ph); in create_dt_mpc8xxx_gpio()
167 qemu_fdt_setprop_cell(fdt, node, "linux,phandle", gpio_ph); in create_dt_mpc8xxx_gpio()
170 qemu_fdt_add_subnode(fdt, poweroff); in create_dt_mpc8xxx_gpio()
171 qemu_fdt_setprop_string(fdt, poweroff, "compatible", "gpio-poweroff"); in create_dt_mpc8xxx_gpio()
172 qemu_fdt_setprop_cells(fdt, poweroff, "gpios", gpio_ph, 0, 0); in create_dt_mpc8xxx_gpio()
178 static void dt_rtc_create(void *fdt, const char *i2c, const char *alias) in dt_rtc_create() argument
183 qemu_fdt_add_subnode(fdt, rtc); in dt_rtc_create()
184 qemu_fdt_setprop_string(fdt, rtc, "compatible", "pericom,pt7c4338"); in dt_rtc_create()
185 qemu_fdt_setprop_cells(fdt, rtc, "reg", offset); in dt_rtc_create()
186 qemu_fdt_setprop_string(fdt, "/aliases", alias, rtc); in dt_rtc_create()
191 static void dt_i2c_create(void *fdt, const char *soc, const char *mpic, in dt_i2c_create() argument
198 qemu_fdt_add_subnode(fdt, i2c); in dt_i2c_create()
199 qemu_fdt_setprop_string(fdt, i2c, "device_type", "i2c"); in dt_i2c_create()
200 qemu_fdt_setprop_string(fdt, i2c, "compatible", "fsl-i2c"); in dt_i2c_create()
201 qemu_fdt_setprop_cells(fdt, i2c, "reg", mmio0, 0x14); in dt_i2c_create()
202 qemu_fdt_setprop_cells(fdt, i2c, "cell-index", 0); in dt_i2c_create()
203 qemu_fdt_setprop_cells(fdt, i2c, "interrupts", irq0, 0x2); in dt_i2c_create()
204 qemu_fdt_setprop_phandle(fdt, i2c, "interrupt-parent", mpic); in dt_i2c_create()
205 qemu_fdt_setprop_cell(fdt, i2c, "#size-cells", 0); in dt_i2c_create()
206 qemu_fdt_setprop_cell(fdt, i2c, "#address-cells", 1); in dt_i2c_create()
207 qemu_fdt_setprop_string(fdt, "/aliases", alias, i2c); in dt_i2c_create()
212 static void dt_sdhc_create(void *fdt, const char *parent, const char *mpic) in dt_sdhc_create() argument
220 qemu_fdt_add_subnode(fdt, name); in dt_sdhc_create()
221 qemu_fdt_setprop(fdt, name, "sdhci,auto-cmd12", NULL, 0); in dt_sdhc_create()
222 qemu_fdt_setprop_phandle(fdt, name, "interrupt-parent", mpic); in dt_sdhc_create()
223 qemu_fdt_setprop_cells(fdt, name, "bus-width", 4); in dt_sdhc_create()
224 qemu_fdt_setprop_cells(fdt, name, "interrupts", irq, 0x2); in dt_sdhc_create()
225 qemu_fdt_setprop_cells(fdt, name, "reg", mmio, size); in dt_sdhc_create()
226 qemu_fdt_setprop_string(fdt, name, "compatible", "fsl,esdhc"); in dt_sdhc_create()
230 void *fdt; member
240 PlatformBusDevice *pbus = data->pbus; in create_devtree_etsec()
245 gchar *node = g_strdup_printf("%s/ethernet@%"PRIx64, data->node, mmio0); in create_devtree_etsec()
246 gchar *group = g_strdup_printf("%s/queue-group", node); in create_devtree_etsec()
247 void *fdt = data->fdt; in create_devtree_etsec() local
254 qemu_fdt_add_subnode(fdt, node); in create_devtree_etsec()
255 qemu_fdt_setprop(fdt, node, "ranges", NULL, 0); in create_devtree_etsec()
256 qemu_fdt_setprop_string(fdt, node, "device_type", "network"); in create_devtree_etsec()
257 qemu_fdt_setprop_string(fdt, node, "compatible", "fsl,etsec2"); in create_devtree_etsec()
258 qemu_fdt_setprop_string(fdt, node, "model", "eTSEC"); in create_devtree_etsec()
259 qemu_fdt_setprop(fdt, node, "local-mac-address", etsec->conf.macaddr.a, 6); in create_devtree_etsec()
260 qemu_fdt_setprop_cells(fdt, node, "fixed-link", 0, 1, 1000, 0, 0); in create_devtree_etsec()
261 qemu_fdt_setprop_cells(fdt, node, "#size-cells", 1); in create_devtree_etsec()
262 qemu_fdt_setprop_cells(fdt, node, "#address-cells", 1); in create_devtree_etsec()
264 qemu_fdt_add_subnode(fdt, group); in create_devtree_etsec()
265 qemu_fdt_setprop_cells(fdt, group, "reg", mmio0, 0x1000); in create_devtree_etsec()
266 qemu_fdt_setprop_cells(fdt, group, "interrupts", in create_devtree_etsec()
267 data->irq_start + irq0, 0x2, in create_devtree_etsec()
268 data->irq_start + irq1, 0x2, in create_devtree_etsec()
269 data->irq_start + irq2, 0x2); in create_devtree_etsec()
299 "num-blocks", in create_devtree_flash()
302 "sector-length", in create_devtree_flash()
309 void *fdt = data->fdt; in create_devtree_flash() local
311 name = g_strdup_printf("%s/nor@%" PRIx64, data->node, flashbase); in create_devtree_flash()
312 qemu_fdt_add_subnode(fdt, name); in create_devtree_flash()
313 qemu_fdt_setprop_string(fdt, name, "compatible", "cfi-flash"); in create_devtree_flash()
314 qemu_fdt_setprop_sized_cells(fdt, name, "reg", in create_devtree_flash()
316 qemu_fdt_setprop_cell(fdt, name, "bank-width", bank_width); in create_devtree_flash()
320 void *fdt, const char *mpic) in platform_bus_create_devtree() argument
323 gchar *node = g_strdup_printf("/platform@%"PRIx64, pmc->platform_bus_base); in platform_bus_create_devtree()
324 const char platcomp[] = "qemu,platform\0simple-bus"; in platform_bus_create_devtree()
325 uint64_t addr = pmc->platform_bus_base; in platform_bus_create_devtree()
326 uint64_t size = pmc->platform_bus_size; in platform_bus_create_devtree()
327 int irq_start = pmc->platform_bus_first_irq; in platform_bus_create_devtree()
333 qemu_fdt_add_subnode(fdt, node); in platform_bus_create_devtree()
334 qemu_fdt_setprop(fdt, node, "compatible", platcomp, sizeof(platcomp)); in platform_bus_create_devtree()
338 qemu_fdt_setprop_cells(fdt, node, "#size-cells", 1); in platform_bus_create_devtree()
339 qemu_fdt_setprop_cells(fdt, node, "#address-cells", 1); in platform_bus_create_devtree()
340 qemu_fdt_setprop_cells(fdt, node, "ranges", 0, addr >> 32, addr, size); in platform_bus_create_devtree()
342 qemu_fdt_setprop_phandle(fdt, node, "interrupt-parent", mpic); in platform_bus_create_devtree()
346 .fdt = fdt, in platform_bus_create_devtree()
350 .pbus = pms->pbus_dev, in platform_bus_create_devtree()
375 unsigned int smp_cpus = machine->smp.cpus; in ppce500_load_device_tree()
378 int ret = -1; in ppce500_load_device_tree()
379 uint64_t mem_reg_property[] = { 0, cpu_to_be64(machine->ram_size) }; in ppce500_load_device_tree()
381 void *fdt; in ppce500_load_device_tree() local
385 char compatible_sb[] = "fsl,mpc8544-immr\0simple-bus"; in ppce500_load_device_tree()
397 0x2000000, 0x0, pmc->pci_mmio_bus_base, in ppce500_load_device_tree()
398 pmc->pci_mmio_base >> 32, pmc->pci_mmio_base, in ppce500_load_device_tree()
402 pmc->pci_pio_base >> 32, pmc->pci_pio_base, in ppce500_load_device_tree()
405 const char *dtb_file = machine->dtb; in ppce500_load_device_tree()
406 const char *toplevel_compat = machine->dt_compatible; in ppce500_load_device_tree()
416 fdt = load_device_tree(filename, &fdt_size); in ppce500_load_device_tree()
418 if (!fdt) { in ppce500_load_device_tree()
424 fdt = create_device_tree(&fdt_size); in ppce500_load_device_tree()
425 if (fdt == NULL) { in ppce500_load_device_tree()
430 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 2); in ppce500_load_device_tree()
431 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 2); in ppce500_load_device_tree()
433 qemu_fdt_add_subnode(fdt, "/memory"); in ppce500_load_device_tree()
434 qemu_fdt_setprop_string(fdt, "/memory", "device_type", "memory"); in ppce500_load_device_tree()
435 qemu_fdt_setprop(fdt, "/memory", "reg", mem_reg_property, in ppce500_load_device_tree()
438 qemu_fdt_add_subnode(fdt, "/chosen"); in ppce500_load_device_tree()
440 ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", in ppce500_load_device_tree()
443 fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n"); in ppce500_load_device_tree()
446 ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", in ppce500_load_device_tree()
449 fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n"); in ppce500_load_device_tree()
454 if (kernel_base != -1ULL) { in ppce500_load_device_tree()
455 qemu_fdt_setprop_cells(fdt, "/chosen", "qemu,boot-kernel", in ppce500_load_device_tree()
460 ret = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", in ppce500_load_device_tree()
461 machine->kernel_cmdline); in ppce500_load_device_tree()
466 qemu_fdt_setprop(fdt, "/chosen", "rng-seed", rng_seed, sizeof(rng_seed)); in ppce500_load_device_tree()
474 qemu_fdt_add_subnode(fdt, "/hypervisor"); in ppce500_load_device_tree()
475 qemu_fdt_setprop_string(fdt, "/hypervisor", "compatible", in ppce500_load_device_tree()
478 qemu_fdt_setprop(fdt, "/hypervisor", "hcall-instructions", in ppce500_load_device_tree()
482 qemu_fdt_setprop(fdt, "/hypervisor", "has-idle", NULL, 0); in ppce500_load_device_tree()
485 clock_freq = pmc->clock_freq; in ppce500_load_device_tree()
486 tb_freq = pmc->tb_freq; in ppce500_load_device_tree()
490 qemu_fdt_add_subnode(fdt, "/cpus"); in ppce500_load_device_tree()
491 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 1); in ppce500_load_device_tree()
492 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0); in ppce500_load_device_tree()
496 for (i = smp_cpus - 1; i >= 0; i--) { in ppce500_load_device_tree()
499 uint64_t cpu_release_addr = pmc->spin_base + (i * 0x20); in ppce500_load_device_tree()
508 qemu_fdt_add_subnode(fdt, cpu_name); in ppce500_load_device_tree()
509 qemu_fdt_setprop_cell(fdt, cpu_name, "clock-frequency", clock_freq); in ppce500_load_device_tree()
510 qemu_fdt_setprop_cell(fdt, cpu_name, "timebase-frequency", tb_freq); in ppce500_load_device_tree()
511 qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu"); in ppce500_load_device_tree()
512 qemu_fdt_setprop_cell(fdt, cpu_name, "reg", i); in ppce500_load_device_tree()
513 qemu_fdt_setprop_cell(fdt, cpu_name, "d-cache-line-size", in ppce500_load_device_tree()
514 env->dcache_line_size); in ppce500_load_device_tree()
515 qemu_fdt_setprop_cell(fdt, cpu_name, "i-cache-line-size", in ppce500_load_device_tree()
516 env->icache_line_size); in ppce500_load_device_tree()
517 qemu_fdt_setprop_cell(fdt, cpu_name, "d-cache-size", 0x8000); in ppce500_load_device_tree()
518 qemu_fdt_setprop_cell(fdt, cpu_name, "i-cache-size", 0x8000); in ppce500_load_device_tree()
519 qemu_fdt_setprop_cell(fdt, cpu_name, "bus-frequency", 0); in ppce500_load_device_tree()
520 if (cpu->cpu_index) { in ppce500_load_device_tree()
521 qemu_fdt_setprop_string(fdt, cpu_name, "status", "disabled"); in ppce500_load_device_tree()
522 qemu_fdt_setprop_string(fdt, cpu_name, "enable-method", in ppce500_load_device_tree()
523 "spin-table"); in ppce500_load_device_tree()
524 qemu_fdt_setprop_u64(fdt, cpu_name, "cpu-release-addr", in ppce500_load_device_tree()
527 qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay"); in ppce500_load_device_tree()
532 qemu_fdt_add_subnode(fdt, "/aliases"); in ppce500_load_device_tree()
534 soc = g_strdup_printf("/soc@%"PRIx64, pmc->ccsrbar_base); in ppce500_load_device_tree()
535 qemu_fdt_add_subnode(fdt, soc); in ppce500_load_device_tree()
536 qemu_fdt_setprop_string(fdt, soc, "device_type", "soc"); in ppce500_load_device_tree()
537 qemu_fdt_setprop(fdt, soc, "compatible", compatible_sb, in ppce500_load_device_tree()
539 qemu_fdt_setprop_cell(fdt, soc, "#address-cells", 1); in ppce500_load_device_tree()
540 qemu_fdt_setprop_cell(fdt, soc, "#size-cells", 1); in ppce500_load_device_tree()
541 qemu_fdt_setprop_cells(fdt, soc, "ranges", 0x0, in ppce500_load_device_tree()
542 pmc->ccsrbar_base >> 32, pmc->ccsrbar_base, in ppce500_load_device_tree()
545 qemu_fdt_setprop_cell(fdt, soc, "bus-frequency", 0); in ppce500_load_device_tree()
548 qemu_fdt_add_subnode(fdt, mpic); in ppce500_load_device_tree()
549 qemu_fdt_setprop_string(fdt, mpic, "device_type", "open-pic"); in ppce500_load_device_tree()
550 qemu_fdt_setprop_string(fdt, mpic, "compatible", "fsl,mpic"); in ppce500_load_device_tree()
551 qemu_fdt_setprop_cells(fdt, mpic, "reg", MPC8544_MPIC_REGS_OFFSET, in ppce500_load_device_tree()
553 qemu_fdt_setprop_cell(fdt, mpic, "#address-cells", 0); in ppce500_load_device_tree()
554 qemu_fdt_setprop_cell(fdt, mpic, "#interrupt-cells", 2); in ppce500_load_device_tree()
555 mpic_ph = qemu_fdt_alloc_phandle(fdt); in ppce500_load_device_tree()
556 qemu_fdt_setprop_cell(fdt, mpic, "phandle", mpic_ph); in ppce500_load_device_tree()
557 qemu_fdt_setprop_cell(fdt, mpic, "linux,phandle", mpic_ph); in ppce500_load_device_tree()
558 qemu_fdt_setprop(fdt, mpic, "interrupt-controller", NULL, 0); in ppce500_load_device_tree()
566 dt_serial_create(fdt, MPC8544_SERIAL1_REGS_OFFSET, in ppce500_load_device_tree()
567 soc, pmc->clock_freq, mpic, "serial1", 1, false); in ppce500_load_device_tree()
571 dt_serial_create(fdt, MPC8544_SERIAL0_REGS_OFFSET, in ppce500_load_device_tree()
572 soc, pmc->clock_freq, mpic, "serial0", 0, true); in ppce500_load_device_tree()
576 dt_i2c_create(fdt, soc, mpic, "i2c"); in ppce500_load_device_tree()
578 dt_rtc_create(fdt, "i2c", "rtc"); in ppce500_load_device_tree()
581 if (pmc->has_esdhc) { in ppce500_load_device_tree()
582 dt_sdhc_create(fdt, soc, mpic); in ppce500_load_device_tree()
585 gutil = g_strdup_printf("%s/global-utilities@%llx", soc, in ppce500_load_device_tree()
587 qemu_fdt_add_subnode(fdt, gutil); in ppce500_load_device_tree()
588 qemu_fdt_setprop_string(fdt, gutil, "compatible", "fsl,mpc8544-guts"); in ppce500_load_device_tree()
589 qemu_fdt_setprop_cells(fdt, gutil, "reg", MPC8544_UTIL_OFFSET, 0x1000); in ppce500_load_device_tree()
590 qemu_fdt_setprop(fdt, gutil, "fsl,has-rstcr", NULL, 0); in ppce500_load_device_tree()
594 qemu_fdt_add_subnode(fdt, msi); in ppce500_load_device_tree()
595 qemu_fdt_setprop_string(fdt, msi, "compatible", "fsl,mpic-msi"); in ppce500_load_device_tree()
596 qemu_fdt_setprop_cells(fdt, msi, "reg", MPC8544_MSI_REGS_OFFSET, 0x200); in ppce500_load_device_tree()
597 msi_ph = qemu_fdt_alloc_phandle(fdt); in ppce500_load_device_tree()
598 qemu_fdt_setprop_cells(fdt, msi, "msi-available-ranges", 0x0, 0x100); in ppce500_load_device_tree()
599 qemu_fdt_setprop_phandle(fdt, msi, "interrupt-parent", mpic); in ppce500_load_device_tree()
600 qemu_fdt_setprop_cells(fdt, msi, "interrupts", in ppce500_load_device_tree()
609 qemu_fdt_setprop_cell(fdt, msi, "phandle", msi_ph); in ppce500_load_device_tree()
610 qemu_fdt_setprop_cell(fdt, msi, "linux,phandle", msi_ph); in ppce500_load_device_tree()
614 pmc->ccsrbar_base + MPC8544_PCI_REGS_OFFSET); in ppce500_load_device_tree()
615 qemu_fdt_add_subnode(fdt, pci); in ppce500_load_device_tree()
616 qemu_fdt_setprop_cell(fdt, pci, "cell-index", 0); in ppce500_load_device_tree()
617 qemu_fdt_setprop_string(fdt, pci, "compatible", "fsl,mpc8540-pci"); in ppce500_load_device_tree()
618 qemu_fdt_setprop_string(fdt, pci, "device_type", "pci"); in ppce500_load_device_tree()
619 qemu_fdt_setprop_cells(fdt, pci, "interrupt-map-mask", 0xf800, 0x0, in ppce500_load_device_tree()
621 pci_map = pci_map_create(fdt, qemu_fdt_get_phandle(fdt, mpic), in ppce500_load_device_tree()
622 pmc->pci_first_slot, pmc->pci_nr_slots, in ppce500_load_device_tree()
624 qemu_fdt_setprop(fdt, pci, "interrupt-map", pci_map, len); in ppce500_load_device_tree()
625 qemu_fdt_setprop_phandle(fdt, pci, "interrupt-parent", mpic); in ppce500_load_device_tree()
626 qemu_fdt_setprop_cells(fdt, pci, "interrupts", 24, 2); in ppce500_load_device_tree()
627 qemu_fdt_setprop_cells(fdt, pci, "bus-range", 0, 255); in ppce500_load_device_tree()
631 qemu_fdt_setprop_cell(fdt, pci, "fsl,msi", msi_ph); in ppce500_load_device_tree()
632 qemu_fdt_setprop(fdt, pci, "ranges", pci_ranges, sizeof(pci_ranges)); in ppce500_load_device_tree()
633 qemu_fdt_setprop_cells(fdt, pci, "reg", in ppce500_load_device_tree()
634 (pmc->ccsrbar_base + MPC8544_PCI_REGS_OFFSET) >> 32, in ppce500_load_device_tree()
635 (pmc->ccsrbar_base + MPC8544_PCI_REGS_OFFSET), in ppce500_load_device_tree()
637 qemu_fdt_setprop_cell(fdt, pci, "clock-frequency", 66666666); in ppce500_load_device_tree()
638 qemu_fdt_setprop_cell(fdt, pci, "#interrupt-cells", 1); in ppce500_load_device_tree()
639 qemu_fdt_setprop_cell(fdt, pci, "#size-cells", 2); in ppce500_load_device_tree()
640 qemu_fdt_setprop_cell(fdt, pci, "#address-cells", 3); in ppce500_load_device_tree()
641 qemu_fdt_setprop_string(fdt, "/aliases", "pci0", pci); in ppce500_load_device_tree()
644 if (pmc->has_mpc8xxx_gpio) { in ppce500_load_device_tree()
645 create_dt_mpc8xxx_gpio(fdt, soc, mpic); in ppce500_load_device_tree()
649 platform_bus_create_devtree(pms, fdt, mpic); in ppce500_load_device_tree()
653 pmc->fixup_devtree(fdt); in ppce500_load_device_tree()
656 qemu_fdt_setprop(fdt, "/", "compatible", toplevel_compat, in ppce500_load_device_tree()
662 cpu_physical_memory_write(addr, fdt, fdt_size); in ppce500_load_device_tree()
664 /* Set machine->fdt for 'dumpdtb' QMP/HMP command */ in ppce500_load_device_tree()
665 g_free(machine->fdt); in ppce500_load_device_tree()
666 machine->fdt = fdt; in ppce500_load_device_tree()
668 g_free(fdt); in ppce500_load_device_tree()
691 ppce500_load_device_tree(p->machine, p->addr, p->initrd_base, in ppce500_reset_device_tree()
692 p->initrd_size, p->kernel_base, p->kernel_size, in ppce500_reset_device_tree()
710 p->machine = machine; in ppce500_prep_device_tree()
711 p->addr = addr; in ppce500_prep_device_tree()
712 p->initrd_base = initrd_base; in ppce500_prep_device_tree()
713 p->initrd_size = initrd_size; in ppce500_prep_device_tree()
714 p->kernel_base = kernel_base; in ppce500_prep_device_tree()
715 p->kernel_size = kernel_size; in ppce500_prep_device_tree()
718 p->notifier.notify = ppce500_init_notify; in ppce500_prep_device_tree()
719 qemu_add_machine_init_done_notifier(&p->notifier); in ppce500_prep_device_tree()
728 return 63 - clz64(size / KiB); in booke206_page_size_to_tlb()
734 tlb->mas1 = booke206_page_size_to_tlb(len) << MAS1_TSIZE_SHIFT; in booke206_set_tlb()
735 tlb->mas1 |= MAS1_VALID; in booke206_set_tlb()
736 tlb->mas2 = va & TARGET_PAGE_MASK; in booke206_set_tlb()
737 tlb->mas7_3 = pa & TARGET_PAGE_MASK; in booke206_set_tlb()
738 tlb->mas7_3 |= MAS3_UR | MAS3_UW | MAS3_UX | MAS3_SR | MAS3_SW | MAS3_SX; in booke206_set_tlb()
743 struct boot_info *bi = env->load_info; in booke206_initial_map_tsize()
749 dt_end = bi->dt_base + bi->dt_size; in booke206_initial_map_tsize()
773 cs->exception_index = EXCP_HLT; in ppce500_cpu_reset_sec()
780 CPUPPCState *env = &cpu->env; in ppce500_cpu_reset()
781 struct boot_info *bi = env->load_info; in ppce500_cpu_reset()
788 cs->halted = 0; in ppce500_cpu_reset()
789 env->gpr[1] = (16 * MiB) - 8; in ppce500_cpu_reset()
790 env->gpr[3] = bi->dt_base; in ppce500_cpu_reset()
791 env->gpr[4] = 0; in ppce500_cpu_reset()
792 env->gpr[5] = 0; in ppce500_cpu_reset()
793 env->gpr[6] = EPAPR_MAGIC; in ppce500_cpu_reset()
794 env->gpr[7] = map_size; in ppce500_cpu_reset()
795 env->gpr[8] = 0; in ppce500_cpu_reset()
796 env->gpr[9] = 0; in ppce500_cpu_reset()
797 env->nip = bi->entry; in ppce500_cpu_reset()
801 env->tlb_dirty = true; in ppce500_cpu_reset()
812 unsigned int smp_cpus = machine->smp.cpus; in ppce500_init_mpic_qemu()
817 qdev_prop_set_uint32(dev, "model", pmc->mpic_version); in ppce500_init_mpic_qemu()
841 qdev_prop_set_uint32(dev, "model", pmc->mpic_version); in ppce500_init_mpic_kvm()
889 s->mmio[0].memory); in ppce500_init_mpic()
910 hwaddr kernel_base = -1LL; in ppce500_init()
924 unsigned int smp_cpus = machine->smp.cpus; in ppce500_init()
941 cpu = POWERPC_CPU(object_new(machine->cpu_type)); in ppce500_init()
942 env = &cpu->env; in ppce500_init()
945 if (env->mmu_model != POWERPC_MMU_BOOKE206) { in ppce500_init()
947 env->mmu_model); in ppce500_init()
953 * when implementing non-kernel boot. in ppce500_init()
955 object_property_set_bool(OBJECT(cs), "start-powered-off", i != 0, in ppce500_init()
967 env->spr_cb[SPR_BOOKE_PIR].default_value = cs->cpu_index = i; in ppce500_init()
968 env->mpic_iack = pmc->ccsrbar_base + MPC8544_MPIC_REGS_OFFSET + 0xa0; in ppce500_init()
970 ppc_booke_timers_init(cpu, pmc->tb_freq, PPC_TIMER_E500); in ppce500_init()
977 env->load_info = boot_info; in ppce500_init()
986 if (!QEMU_IS_ALIGNED(machine->ram_size, RAM_SIZES_ALIGN)) { in ppce500_init()
992 memory_region_add_subregion(address_space_mem, 0, machine->ram); in ppce500_init()
994 dev = qdev_new("e500-ccsr"); in ppce500_init()
996 object_property_add_child(OBJECT(machine), "e500-ccsr", OBJECT(dev)); in ppce500_init()
999 memory_region_add_subregion(address_space_mem, pmc->ccsrbar_base, in ppce500_init()
1019 dev = qdev_new("mpc-i2c"); in ppce500_init()
1029 if (pmc->has_esdhc) { in ppce500_init()
1040 * - SD Host Controller Specification Version 2.0 Part A2 in ppce500_init()
1044 qdev_prop_set_uint8(dev, "sd-spec-version", 2); in ppce500_init()
1055 dev = qdev_new("mpc8544-guts"); in ppce500_init()
1062 dev = qdev_new("e500-pcihost"); in ppce500_init()
1063 object_property_add_child(OBJECT(machine), "pci-host", OBJECT(dev)); in ppce500_init()
1064 qdev_prop_set_uint32(dev, "first_slot", pmc->pci_first_slot); in ppce500_init()
1081 pci_init_nic_devices(pci_bus, mc->default_nic); in ppce500_init()
1085 sysbus_create_simple("e500-spin", pmc->spin_base, NULL); in ppce500_init()
1087 if (pmc->has_mpc8xxx_gpio) { in ppce500_init()
1104 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE); in ppce500_init()
1105 qdev_prop_set_uint32(dev, "num_irqs", pmc->platform_bus_num_irqs); in ppce500_init()
1106 qdev_prop_set_uint32(dev, "mmio_size", pmc->platform_bus_size); in ppce500_init()
1108 pms->pbus_dev = PLATFORM_BUS_DEVICE(dev); in ppce500_init()
1110 s = SYS_BUS_DEVICE(pms->pbus_dev); in ppce500_init()
1111 for (i = 0; i < pmc->platform_bus_num_irqs; i++) { in ppce500_init()
1112 int irqn = pmc->platform_bus_first_irq + i; in ppce500_init()
1117 pmc->platform_bus_base, in ppce500_init()
1118 &pms->pbus_dev->mmio); in ppce500_init()
1124 uint64_t mmio_size = memory_region_size(&pms->pbus_dev->mmio); in ppce500_init()
1147 qdev_prop_set_uint32(dev, "num-blocks", size / sector_len); in ppce500_init()
1148 qdev_prop_set_uint64(dev, "sector-length", sector_len); in ppce500_init()
1150 qdev_prop_set_bit(dev, "big-endian", true); in ppce500_init()
1158 memory_region_add_subregion(&pms->pbus_dev->mmio, 0, in ppce500_init()
1167 * -kernel | -bios | payload in ppce500_init()
1168 * ---------+-------+--------- in ppce500_init()
1169 * N | Y | u-boot in ppce500_init()
1170 * N | N | u-boot in ppce500_init()
1171 * Y | Y | u-boot in ppce500_init()
1175 * -kernel to users but allows them to run through u-boot as well. in ppce500_init()
1178 if (machine->firmware == NULL) { in ppce500_init()
1179 if (machine->kernel_filename) { in ppce500_init()
1180 payload_name = machine->kernel_filename; in ppce500_init()
1183 payload_name = "u-boot.e500"; in ppce500_init()
1186 payload_name = machine->firmware; in ppce500_init()
1221 /* u-boot occupies memory up to 32MB, so load blobs above */ in ppce500_init()
1225 /* Load bare kernel only if no bios/u-boot has been provided */ in ppce500_init()
1226 if (machine->kernel_filename && !kernel_as_payload) { in ppce500_init()
1228 kernel_size = load_image_targphys(machine->kernel_filename, in ppce500_init()
1230 machine->ram_size - cur_base); in ppce500_init()
1233 machine->kernel_filename); in ppce500_init()
1241 if (machine->initrd_filename) { in ppce500_init()
1243 initrd_size = load_image_targphys(machine->initrd_filename, initrd_base, in ppce500_init()
1244 machine->ram_size - initrd_base); in ppce500_init()
1248 machine->initrd_filename); in ppce500_init()
1262 if (dt_base + DTB_MAX_SIZE > machine->ram_size) { in ppce500_init()
1276 boot_info->entry = bios_entry; in ppce500_init()
1277 boot_info->dt_base = dt_base; in ppce500_init()
1278 boot_info->dt_size = dt_size; in ppce500_init()
1284 memory_region_init(&ccsr->ccsr_space, obj, "e500-ccsr", in e500_ccsr_initfn()
1286 sysbus_init_mmio(SYS_BUS_DEVICE(ccsr), &ccsr->ccsr_space); in e500_ccsr_initfn()