Lines Matching +full:0 +full:- +full:dev
38 # define PCIE_DPRINTF(fmt, ...) do {} while (0)
40 #define PCIE_DEV_PRINTF(dev, fmt, ...) \ argument
41 PCIE_DPRINTF("%s:%x "fmt, (dev)->name, (dev)->devfn, ## __VA_ARGS__)
71 pcie_cap_v1_fill(PCIDevice *dev, uint8_t port, uint8_t type, uint8_t version) in pcie_cap_v1_fill() argument
73 uint8_t *exp_cap = dev->config + dev->exp.exp_cap; in pcie_cap_v1_fill()
74 uint8_t *cmask = dev->cmask + dev->exp.exp_cap; in pcie_cap_v1_fill()
77 interrupt message number defaults to 0 */ in pcie_cap_v1_fill()
83 * table 7-12: in pcie_cap_v1_fill()
91 if (dev->cap_present & QEMU_PCIE_EXT_TAG) { in pcie_cap_v1_fill()
111 pci_set_word(cmask + PCI_EXP_LNKSTA, 0); in pcie_cap_v1_fill()
143 pci_long_test_and_clear_mask(exp_cap + PCI_EXP_LNKCAP2, ~0U); in pcie_cap_fill_lnk()
163 void pcie_cap_fill_link_ep_usp(PCIDevice *dev, PCIExpLinkWidth width, in pcie_cap_fill_link_ep_usp() argument
166 uint8_t *exp_cap = dev->config + dev->exp.exp_cap; in pcie_cap_fill_link_ep_usp()
181 static void pcie_cap_fill_slot_lnk(PCIDevice *dev) in pcie_cap_fill_slot_lnk() argument
183 PCIESlot *s = (PCIESlot *)object_dynamic_cast(OBJECT(dev), TYPE_PCIE_SLOT); in pcie_cap_fill_slot_lnk()
184 uint8_t *exp_cap = dev->config + dev->exp.exp_cap; in pcie_cap_fill_slot_lnk()
196 if (s->width > QEMU_PCI_EXP_LNK_X1 || in pcie_cap_fill_slot_lnk()
197 s->speed > QEMU_PCI_EXP_LNK_2_5GT) { in pcie_cap_fill_slot_lnk()
202 if (s->speed > QEMU_PCI_EXP_LNK_2_5GT) { in pcie_cap_fill_slot_lnk()
204 * Hot-plug capable downstream ports and downstream ports supporting in pcie_cap_fill_slot_lnk()
207 * we also hardwire to 1b here. 2.5GT/s hot-plug slots should also in pcie_cap_fill_slot_lnk()
215 pcie_cap_fill_lnk(exp_cap, s->width, s->speed); in pcie_cap_fill_slot_lnk()
218 int pcie_cap_init(PCIDevice *dev, uint8_t offset, in pcie_cap_init() argument
226 assert(pci_is_express(dev)); in pcie_cap_init()
228 pos = pci_add_capability(dev, PCI_CAP_ID_EXP, offset, in pcie_cap_init()
230 if (pos < 0) { in pcie_cap_init()
233 dev->exp.exp_cap = pos; in pcie_cap_init()
234 exp_cap = dev->config + pos; in pcie_cap_init()
237 pcie_cap_v1_fill(dev, port, type, PCI_EXP_FLAGS_VER2); in pcie_cap_init()
240 pcie_cap_fill_slot_lnk(dev); in pcie_cap_init()
246 pci_set_word(dev->wmask + pos + PCI_EXP_DEVCTL2, PCI_EXP_DEVCTL2_EETLPPB); in pcie_cap_init()
248 if (dev->cap_present & QEMU_PCIE_EXTCAP_INIT) { in pcie_cap_init()
249 /* read-only to behave like a 'NULL' Extended Capability Header */ in pcie_cap_init()
250 pci_set_long(dev->wmask + PCI_CONFIG_SPACE_SIZE, 0); in pcie_cap_init()
256 int pcie_cap_v1_init(PCIDevice *dev, uint8_t offset, uint8_t type, in pcie_cap_v1_init() argument
263 assert(pci_is_express(dev)); in pcie_cap_v1_init()
265 pos = pci_add_capability(dev, PCI_CAP_ID_EXP, offset, in pcie_cap_v1_init()
267 if (pos < 0) { in pcie_cap_v1_init()
271 dev->exp.exp_cap = pos; in pcie_cap_v1_init()
273 pcie_cap_v1_fill(dev, port, type, PCI_EXP_FLAGS_VER1); in pcie_cap_v1_init()
279 pcie_endpoint_cap_common_init(PCIDevice *dev, uint8_t offset, uint8_t cap_size) in pcie_endpoint_cap_common_init() argument
290 if (pci_bus_is_express(pci_get_bus(dev)) in pcie_endpoint_cap_common_init()
291 && pci_bus_is_root(pci_get_bus(dev))) { in pcie_endpoint_cap_common_init()
296 return pcie_cap_v1_init(dev, offset, type, 0); in pcie_endpoint_cap_common_init()
298 ret = pcie_cap_init(dev, offset, type, 0, &local_err); in pcie_endpoint_cap_common_init()
300 if (ret < 0) { in pcie_endpoint_cap_common_init()
308 int pcie_endpoint_cap_init(PCIDevice *dev, uint8_t offset) in pcie_endpoint_cap_init() argument
310 return pcie_endpoint_cap_common_init(dev, offset, PCI_EXP_VER2_SIZEOF); in pcie_endpoint_cap_init()
313 int pcie_endpoint_cap_v1_init(PCIDevice *dev, uint8_t offset) in pcie_endpoint_cap_v1_init() argument
315 return pcie_endpoint_cap_common_init(dev, offset, PCI_EXP_VER1_SIZEOF); in pcie_endpoint_cap_v1_init()
318 void pcie_cap_exit(PCIDevice *dev) in pcie_cap_exit() argument
320 pci_del_capability(dev, PCI_CAP_ID_EXP, PCI_EXP_VER2_SIZEOF); in pcie_cap_exit()
323 void pcie_cap_v1_exit(PCIDevice *dev) in pcie_cap_v1_exit() argument
325 pci_del_capability(dev, PCI_CAP_ID_EXP, PCI_EXP_VER1_SIZEOF); in pcie_cap_v1_exit()
328 uint8_t pcie_cap_get_type(const PCIDevice *dev) in pcie_cap_get_type() argument
330 uint32_t pos = dev->exp.exp_cap; in pcie_cap_get_type()
331 assert(pos > 0); in pcie_cap_get_type()
332 return (pci_get_word(dev->config + pos + PCI_EXP_FLAGS) & in pcie_cap_get_type()
336 uint8_t pcie_cap_get_version(const PCIDevice *dev) in pcie_cap_get_version() argument
338 uint32_t pos = dev->exp.exp_cap; in pcie_cap_get_version()
339 assert(pos > 0); in pcie_cap_get_version()
340 return pci_get_word(dev->config + pos + PCI_EXP_FLAGS) & PCI_EXP_FLAGS_VERS; in pcie_cap_get_version()
343 /* MSI/MSI-X */
346 void pcie_cap_flags_set_vector(PCIDevice *dev, uint8_t vector) in pcie_cap_flags_set_vector() argument
348 uint8_t *exp_cap = dev->config + dev->exp.exp_cap; in pcie_cap_flags_set_vector()
355 uint8_t pcie_cap_flags_get_vector(PCIDevice *dev) in pcie_cap_flags_get_vector() argument
357 return (pci_get_word(dev->config + dev->exp.exp_cap + PCI_EXP_FLAGS) & in pcie_cap_flags_get_vector()
361 void pcie_cap_deverr_init(PCIDevice *dev) in pcie_cap_deverr_init() argument
363 uint32_t pos = dev->exp.exp_cap; in pcie_cap_deverr_init()
364 pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_DEVCAP, in pcie_cap_deverr_init()
366 pci_long_test_and_set_mask(dev->wmask + pos + PCI_EXP_DEVCTL, in pcie_cap_deverr_init()
369 pci_long_test_and_set_mask(dev->w1cmask + pos + PCI_EXP_DEVSTA, in pcie_cap_deverr_init()
374 void pcie_cap_deverr_reset(PCIDevice *dev) in pcie_cap_deverr_reset() argument
376 uint8_t *devctl = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL; in pcie_cap_deverr_reset()
382 void pcie_cap_lnkctl_init(PCIDevice *dev) in pcie_cap_lnkctl_init() argument
384 uint32_t pos = dev->exp.exp_cap; in pcie_cap_lnkctl_init()
385 pci_long_test_and_set_mask(dev->wmask + pos + PCI_EXP_LNKCTL, in pcie_cap_lnkctl_init()
389 void pcie_cap_lnkctl_reset(PCIDevice *dev) in pcie_cap_lnkctl_reset() argument
391 uint8_t *lnkctl = dev->config + dev->exp.exp_cap + PCI_EXP_LNKCTL; in pcie_cap_lnkctl_reset()
396 static void hotplug_event_update_event_status(PCIDevice *dev) in hotplug_event_update_event_status() argument
398 uint32_t pos = dev->exp.exp_cap; in hotplug_event_update_event_status()
399 uint8_t *exp_cap = dev->config + pos; in hotplug_event_update_event_status()
403 dev->exp.hpev_notified = (sltctl & PCI_EXP_SLTCTL_HPIE) && in hotplug_event_update_event_status()
407 static void hotplug_event_notify(PCIDevice *dev) in hotplug_event_notify() argument
409 bool prev = dev->exp.hpev_notified; in hotplug_event_notify()
411 hotplug_event_update_event_status(dev); in hotplug_event_notify()
413 if (prev == dev->exp.hpev_notified) { in hotplug_event_notify()
420 * The Port may optionally send an MSI when there are hot-plug events that in hotplug_event_notify()
423 if (msix_enabled(dev)) { in hotplug_event_notify()
424 msix_notify(dev, pcie_cap_flags_get_vector(dev)); in hotplug_event_notify()
425 } else if (msi_enabled(dev)) { in hotplug_event_notify()
426 msi_notify(dev, pcie_cap_flags_get_vector(dev)); in hotplug_event_notify()
427 } else if (pci_intx(dev) != -1) { in hotplug_event_notify()
428 pci_set_irq(dev, dev->exp.hpev_notified); in hotplug_event_notify()
432 static void hotplug_event_clear(PCIDevice *dev) in hotplug_event_clear() argument
434 hotplug_event_update_event_status(dev); in hotplug_event_clear()
435 if (!msix_enabled(dev) && !msi_enabled(dev) && pci_intx(dev) != -1 && in hotplug_event_clear()
436 !dev->exp.hpev_notified) { in hotplug_event_clear()
437 pci_irq_deassert(dev); in hotplug_event_clear()
441 void pcie_cap_slot_enable_power(PCIDevice *dev) in pcie_cap_slot_enable_power() argument
443 uint8_t *exp_cap = dev->config + dev->exp.exp_cap; in pcie_cap_slot_enable_power()
452 static void pcie_set_power_device(PCIBus *bus, PCIDevice *dev, void *opaque) in pcie_set_power_device() argument
456 pci_set_power(dev, *power); in pcie_set_power_device()
461 uint8_t *exp_cap = hotplug_dev->config + hotplug_dev->exp.exp_cap; in pcie_cap_update_power()
477 * A PCI Express Hot-Plug Event has occurred, so update slot status register
480 * 6.7.3 PCI Express Hot-Plug Events
481 * 6.7.3.4 Software Notification of Hot-Plug Events
483 static void pcie_cap_slot_event(PCIDevice *dev, PCIExpressHotPlugEvent event) in pcie_cap_slot_event() argument
485 /* Minor optimization: if nothing changed - no event is needed. */ in pcie_cap_slot_event()
486 if (pci_word_test_and_set_mask(dev->config + dev->exp.exp_cap + in pcie_cap_slot_event()
490 hotplug_event_notify(dev); in pcie_cap_slot_event()
493 static void pcie_cap_slot_plug_common(PCIDevice *hotplug_dev, DeviceState *dev, in pcie_cap_slot_plug_common() argument
496 uint8_t *exp_cap = hotplug_dev->config + hotplug_dev->exp.exp_cap; in pcie_cap_slot_plug_common()
499 PCIE_DEV_PRINTF(PCI_DEVICE(dev), "hotplug state: 0x%x\n", sltsta); in pcie_cap_slot_plug_common()
508 void pcie_cap_slot_pre_plug_cb(HotplugHandler *hotplug_dev, DeviceState *dev, in pcie_cap_slot_pre_plug_cb() argument
512 uint8_t *exp_cap = hotplug_pdev->config + hotplug_pdev->exp.exp_cap; in pcie_cap_slot_pre_plug_cb()
515 /* Check if hot-plug is disabled on the slot */ in pcie_cap_slot_pre_plug_cb()
516 if (dev->hotplugged && (sltcap & PCI_EXP_SLTCAP_HPC) == 0) { in pcie_cap_slot_pre_plug_cb()
517 error_setg(errp, "Hot-plug failed: unsupported by the port device '%s'", in pcie_cap_slot_pre_plug_cb()
518 DEVICE(hotplug_pdev)->id); in pcie_cap_slot_pre_plug_cb()
522 pcie_cap_slot_plug_common(PCI_DEVICE(hotplug_dev), dev, errp); in pcie_cap_slot_pre_plug_cb()
525 void pcie_cap_slot_plug_cb(HotplugHandler *hotplug_dev, DeviceState *dev, in pcie_cap_slot_plug_cb() argument
529 uint8_t *exp_cap = hotplug_pdev->config + hotplug_pdev->exp.exp_cap; in pcie_cap_slot_plug_cb()
530 PCIDevice *pci_dev = PCI_DEVICE(dev); in pcie_cap_slot_plug_cb()
541 if (!dev->hotplugged) { in pcie_cap_slot_plug_cb()
544 if (pci_dev->cap_present & QEMU_PCIE_LNKSTA_DLLLA || in pcie_cap_slot_plug_cb()
553 /* To enable multifunction hot-plug, we just ensure the function in pcie_cap_slot_plug_cb()
554 * 0 added last. When function 0 is added, we set the sltsta and in pcie_cap_slot_plug_cb()
560 if (pci_dev->cap_present & QEMU_PCIE_LNKSTA_DLLLA || in pcie_cap_slot_plug_cb()
571 void pcie_cap_slot_unplug_cb(HotplugHandler *hotplug_dev, DeviceState *dev, in pcie_cap_slot_unplug_cb() argument
574 qdev_unrealize(dev); in pcie_cap_slot_unplug_cb()
577 static void pcie_unplug_device(PCIBus *bus, PCIDevice *dev, void *opaque) in pcie_unplug_device() argument
579 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(DEVICE(dev)); in pcie_unplug_device()
581 if (dev->partially_hotplugged) { in pcie_unplug_device()
582 dev->qdev.pending_deleted_event = false; in pcie_unplug_device()
585 hotplug_handler_unplug(hotplug_ctrl, DEVICE(dev), &error_abort); in pcie_unplug_device()
586 object_unparent(OBJECT(dev)); in pcie_unplug_device()
589 static void pcie_cap_slot_do_unplug(PCIDevice *dev) in pcie_cap_slot_do_unplug() argument
591 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev)); in pcie_cap_slot_do_unplug()
592 uint8_t *exp_cap = dev->config + dev->exp.exp_cap; in pcie_cap_slot_do_unplug()
599 if (dev->cap_present & QEMU_PCIE_LNKSTA_DLLLA || in pcie_cap_slot_do_unplug()
609 DeviceState *dev, Error **errp) in pcie_cap_slot_unplug_request_cb() argument
612 PCIDevice *pci_dev = PCI_DEVICE(dev); in pcie_cap_slot_unplug_request_cb()
615 uint8_t *exp_cap = hotplug_pdev->config + hotplug_pdev->exp.exp_cap; in pcie_cap_slot_unplug_request_cb()
619 /* Check if hot-unplug is disabled on the slot */ in pcie_cap_slot_unplug_request_cb()
620 if ((sltcap & PCI_EXP_SLTCAP_HPC) == 0) { in pcie_cap_slot_unplug_request_cb()
621 error_setg(errp, "Hot-unplug failed: " in pcie_cap_slot_unplug_request_cb()
623 DEVICE(hotplug_pdev)->id); in pcie_cap_slot_unplug_request_cb()
627 pcie_cap_slot_plug_common(hotplug_pdev, dev, &local_err); in pcie_cap_slot_unplug_request_cb()
634 error_setg(errp, "Hot-unplug failed: " in pcie_cap_slot_unplug_request_cb()
639 dev->pending_deleted_event = true; in pcie_cap_slot_unplug_request_cb()
640 dev->pending_deleted_expires_ms = in pcie_cap_slot_unplug_request_cb()
643 /* In case user cancel the operation of multi-function hot-add, in pcie_cap_slot_unplug_request_cb()
647 if (pci_dev->devfn && in pcie_cap_slot_unplug_request_cb()
648 !bus->devices[0]) { in pcie_cap_slot_unplug_request_cb()
655 /* slot is powered off -> unplug without round-trip to the guest */ in pcie_cap_slot_unplug_request_cb()
668 void pcie_cap_slot_init(PCIDevice *dev, PCIESlot *s) in pcie_cap_slot_init() argument
670 uint32_t pos = dev->exp.exp_cap; in pcie_cap_slot_init()
672 pci_word_test_and_set_mask(dev->config + pos + PCI_EXP_FLAGS, in pcie_cap_slot_init()
675 pci_long_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCAP, in pcie_cap_slot_init()
677 pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCAP, in pcie_cap_slot_init()
678 (s->slot << PCI_EXP_SLTCAP_PSN_SHIFT) | in pcie_cap_slot_init()
685 * Expose native hot-plug on all bridges if hot-plug is enabled on the slot. in pcie_cap_slot_init()
688 if (s->hotplug && in pcie_cap_slot_init()
689 (!s->hide_native_hotplug_cap || DEVICE(dev)->hotplugged)) { in pcie_cap_slot_init()
690 pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCAP, in pcie_cap_slot_init()
695 if (dev->cap_present & QEMU_PCIE_SLTCAP_PCP) { in pcie_cap_slot_init()
696 pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCAP, in pcie_cap_slot_init()
698 pci_word_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCTL, in pcie_cap_slot_init()
700 pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL, in pcie_cap_slot_init()
704 pci_word_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCTL, in pcie_cap_slot_init()
707 pci_word_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCTL, in pcie_cap_slot_init()
710 pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL, in pcie_cap_slot_init()
717 /* Although reading PCI_EXP_SLTCTL_EIC returns always 0, in pcie_cap_slot_init()
719 * pcie_cap_slot_write_config() test-and-clear the bit, so in pcie_cap_slot_init()
720 * this bit always returns 0 to the guest. in pcie_cap_slot_init()
722 pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL, in pcie_cap_slot_init()
725 pci_word_test_and_set_mask(dev->w1cmask + pos + PCI_EXP_SLTSTA, in pcie_cap_slot_init()
728 /* Avoid migration abortion when this device hot-removed by guest */ in pcie_cap_slot_init()
729 pci_word_test_and_clear_mask(dev->cmask + pos + PCI_EXP_SLTSTA, in pcie_cap_slot_init()
732 dev->exp.hpev_notified = false; in pcie_cap_slot_init()
734 qbus_set_hotplug_handler(BUS(pci_bridge_get_sec_bus(PCI_BRIDGE(dev))), in pcie_cap_slot_init()
735 OBJECT(dev)); in pcie_cap_slot_init()
738 void pcie_cap_slot_reset(PCIDevice *dev) in pcie_cap_slot_reset() argument
740 uint8_t *exp_cap = dev->config + dev->exp.exp_cap; in pcie_cap_slot_reset()
741 uint8_t port_type = pcie_cap_get_type(dev); in pcie_cap_slot_reset()
746 PCIE_DEV_PRINTF(dev, "reset\n"); in pcie_cap_slot_reset()
760 if (dev->cap_present & QEMU_PCIE_SLTCAP_PCP) { in pcie_cap_slot_reset()
761 /* Downstream ports enforce device number 0. */ in pcie_cap_slot_reset()
762 bool populated = pci_bridge_get_sec_bus(PCI_BRIDGE(dev))->devices[0]; in pcie_cap_slot_reset()
785 pcie_cap_update_power(dev); in pcie_cap_slot_reset()
786 hotplug_event_update_event_status(dev); in pcie_cap_slot_reset()
789 void pcie_cap_slot_get(PCIDevice *dev, uint16_t *slt_ctl, uint16_t *slt_sta) in pcie_cap_slot_get() argument
791 uint32_t pos = dev->exp.exp_cap; in pcie_cap_slot_get()
792 uint8_t *exp_cap = dev->config + pos; in pcie_cap_slot_get()
797 static void find_child_fn(PCIBus *bus, PCIDevice *dev, void *opaque) in find_child_fn() argument
802 *child = dev; in find_child_fn()
809 static PCIDevice *pcie_cap_slot_find_child(PCIDevice *dev) in pcie_cap_slot_find_child() argument
811 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev)); in pcie_cap_slot_find_child()
819 void pcie_cap_slot_write_config(PCIDevice *dev, in pcie_cap_slot_write_config() argument
823 uint32_t pos = dev->exp.exp_cap; in pcie_cap_slot_write_config()
824 uint8_t *exp_cap = dev->config + pos; in pcie_cap_slot_write_config()
832 * As a work-around, detect this and revert status to what it was in pcie_cap_slot_write_config()
847 hotplug_event_clear(dev); in pcie_cap_slot_write_config()
858 PCIE_DEV_PRINTF(dev, "PCI_EXP_SLTCTL_EIC: " in pcie_cap_slot_write_config()
859 "sltsta -> 0x%02"PRIx16"\n", in pcie_cap_slot_write_config()
864 DeviceState *parent = DEVICE(dev); in pcie_cap_slot_write_config()
865 DeviceState *child = DEVICE(pcie_cap_slot_find_child(dev)); in pcie_cap_slot_write_config()
868 parent->canonical_path, in pcie_cap_slot_write_config()
869 child ? child->canonical_path : "no-child", in pcie_cap_slot_write_config()
890 pcie_cap_slot_do_unplug(dev); in pcie_cap_slot_write_config()
892 pcie_cap_update_power(dev); in pcie_cap_slot_write_config()
894 hotplug_event_notify(dev); in pcie_cap_slot_write_config()
899 * Software issues a command to a hot-plug capable Downstream Port by in pcie_cap_slot_write_config()
912 pcie_cap_slot_event(dev, PCI_EXP_HP_EV_CCI); in pcie_cap_slot_write_config()
917 PCIDevice *dev = opaque; in pcie_cap_slot_post_load() local
918 hotplug_event_update_event_status(dev); in pcie_cap_slot_post_load()
919 pcie_cap_update_power(dev); in pcie_cap_slot_post_load()
920 return 0; in pcie_cap_slot_post_load()
923 void pcie_cap_slot_push_attention_button(PCIDevice *dev) in pcie_cap_slot_push_attention_button() argument
925 pcie_cap_slot_event(dev, PCI_EXP_HP_EV_ABP); in pcie_cap_slot_push_attention_button()
929 void pcie_cap_root_init(PCIDevice *dev) in pcie_cap_root_init() argument
931 pci_set_word(dev->wmask + dev->exp.exp_cap + PCI_EXP_RTCTL, in pcie_cap_root_init()
936 void pcie_cap_root_reset(PCIDevice *dev) in pcie_cap_root_reset() argument
938 pci_set_word(dev->config + dev->exp.exp_cap + PCI_EXP_RTCTL, 0); in pcie_cap_root_reset()
942 void pcie_cap_flr_init(PCIDevice *dev) in pcie_cap_flr_init() argument
944 pci_long_test_and_set_mask(dev->config + dev->exp.exp_cap + PCI_EXP_DEVCAP, in pcie_cap_flr_init()
947 /* Although reading BCR_FLR returns always 0, in pcie_cap_flr_init()
949 * pcie_cap_flr_write_config() test-and-clear the bit, so in pcie_cap_flr_init()
950 * this bit always returns 0 to the guest. in pcie_cap_flr_init()
952 pci_word_test_and_set_mask(dev->wmask + dev->exp.exp_cap + PCI_EXP_DEVCTL, in pcie_cap_flr_init()
956 void pcie_cap_flr_write_config(PCIDevice *dev, in pcie_cap_flr_write_config() argument
959 uint8_t *devctl = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL; in pcie_cap_flr_write_config()
963 pci_device_reset(dev); in pcie_cap_flr_write_config()
968 /* Alternative Routing-ID Interpretation (ARI)
971 void pcie_cap_arifwd_init(PCIDevice *dev) in pcie_cap_arifwd_init() argument
973 uint32_t pos = dev->exp.exp_cap; in pcie_cap_arifwd_init()
974 pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_DEVCAP2, in pcie_cap_arifwd_init()
976 pci_long_test_and_set_mask(dev->wmask + pos + PCI_EXP_DEVCTL2, in pcie_cap_arifwd_init()
980 void pcie_cap_arifwd_reset(PCIDevice *dev) in pcie_cap_arifwd_reset() argument
982 uint8_t *devctl2 = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL2; in pcie_cap_arifwd_reset()
986 bool pcie_cap_is_arifwd_enabled(const PCIDevice *dev) in pcie_cap_is_arifwd_enabled() argument
988 if (!pci_is_express(dev)) { in pcie_cap_is_arifwd_enabled()
991 if (!dev->exp.exp_cap) { in pcie_cap_is_arifwd_enabled()
995 return pci_get_long(dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL2) & in pcie_cap_is_arifwd_enabled()
1007 /* Passing a cap_id value > 0xffff will return 0 and put end of list in prev */
1008 static uint16_t pcie_find_capability_list(PCIDevice *dev, uint32_t cap_id, in pcie_find_capability_list() argument
1011 uint16_t prev = 0; in pcie_find_capability_list()
1013 uint32_t header = pci_get_long(dev->config + PCI_CONFIG_SPACE_SIZE); in pcie_find_capability_list()
1017 next = 0; in pcie_find_capability_list()
1024 assert(next <= PCIE_CONFIG_SPACE_SIZE - 8); in pcie_find_capability_list()
1026 header = pci_get_long(dev->config + next); in pcie_find_capability_list()
1039 uint16_t pcie_find_capability(PCIDevice *dev, uint16_t cap_id) in pcie_find_capability() argument
1041 return pcie_find_capability_list(dev, cap_id, NULL); in pcie_find_capability()
1044 static void pcie_ext_cap_set_next(PCIDevice *dev, uint16_t pos, uint16_t next) in pcie_ext_cap_set_next() argument
1046 uint32_t header = pci_get_long(dev->config + pos); in pcie_ext_cap_set_next()
1047 assert(!(next & (PCI_EXT_CAP_ALIGN - 1))); in pcie_ext_cap_set_next()
1050 pci_set_long(dev->config + pos, header); in pcie_ext_cap_set_next()
1058 void pcie_add_capability(PCIDevice *dev, in pcie_add_capability() argument
1066 assert(pci_is_express(dev)); in pcie_add_capability()
1072 * 0xffffffff is not a valid cap id (it's a 16 bit field). use in pcie_add_capability()
1075 pcie_find_capability_list(dev, 0xffffffff, &prev); in pcie_add_capability()
1077 pcie_ext_cap_set_next(dev, prev, offset); in pcie_add_capability()
1079 pci_set_long(dev->config + offset, PCI_EXT_CAP(cap_id, cap_ver, 0)); in pcie_add_capability()
1081 /* Make capability read-only by default */ in pcie_add_capability()
1082 memset(dev->wmask + offset, 0, size); in pcie_add_capability()
1083 memset(dev->w1cmask + offset, 0, size); in pcie_add_capability()
1085 memset(dev->cmask + offset, 0xFF, size); in pcie_add_capability()
1090 * downstream device. If downstream device is not present, re-write with the
1102 PCIDevice *target = bus->devices[0]; in pcie_sync_bridge_lnk()
1103 uint8_t *exp_cap = bridge_dev->config + bridge_dev->exp.exp_cap; in pcie_sync_bridge_lnk()
1106 if (!target || !target->exp.exp_cap) { in pcie_sync_bridge_lnk()
1109 lnksta = target->config_read(target, in pcie_sync_bridge_lnk()
1110 target->exp.exp_cap + PCI_EXP_LNKSTA, in pcie_sync_bridge_lnk()
1143 void pcie_ari_init(PCIDevice *dev, uint16_t offset) in pcie_ari_init() argument
1145 uint16_t nextfn = dev->cap_present & QEMU_PCIE_ARI_NEXTFN_1 ? 1 : 0; in pcie_ari_init()
1147 pcie_add_capability(dev, PCI_EXT_CAP_ID_ARI, PCI_ARI_VER, in pcie_ari_init()
1149 pci_set_long(dev->config + offset + PCI_ARI_CAP, (nextfn & 0xff) << 8); in pcie_ari_init()
1152 void pcie_dev_ser_num_init(PCIDevice *dev, uint16_t offset, uint64_t ser_num) in pcie_dev_ser_num_init() argument
1157 pcie_add_capability(dev, PCI_EXT_CAP_ID_DSN, pci_dsn_ver, offset, in pcie_dev_ser_num_init()
1159 pci_set_quad(dev->config + offset + pci_dsn_cap, ser_num); in pcie_dev_ser_num_init()
1162 void pcie_ats_init(PCIDevice *dev, uint16_t offset, bool aligned) in pcie_ats_init() argument
1164 pcie_add_capability(dev, PCI_EXT_CAP_ID_ATS, 0x1, in pcie_ats_init()
1167 dev->exp.ats_cap = offset; in pcie_ats_init()
1169 /* Invalidate Queue Depth 0 */ in pcie_ats_init()
1171 pci_set_word(dev->config + offset + PCI_ATS_CAP, in pcie_ats_init()
1174 /* STU 0, Disabled by default */ in pcie_ats_init()
1175 pci_set_word(dev->config + offset + PCI_ATS_CTRL, 0); in pcie_ats_init()
1177 pci_set_word(dev->wmask + dev->exp.ats_cap + PCI_ATS_CTRL, 0x800f); in pcie_ats_init()
1181 void pcie_acs_init(PCIDevice *dev, uint16_t offset) in pcie_acs_init() argument
1183 bool is_downstream = pci_is_express_downstream_port(dev); in pcie_acs_init()
1184 uint16_t cap_bits = 0; in pcie_acs_init()
1188 (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) || in pcie_acs_init()
1189 PCI_FUNC(dev->devfn)); in pcie_acs_init()
1191 pcie_add_capability(dev, PCI_EXT_CAP_ID_ACS, PCI_ACS_VER, offset, in pcie_acs_init()
1193 dev->exp.acs_cap = offset; in pcie_acs_init()
1201 * peer-to-peer between functions and thus omitted here. in pcie_acs_init()
1207 pci_set_word(dev->config + offset + PCI_ACS_CAP, cap_bits); in pcie_acs_init()
1208 pci_set_word(dev->wmask + offset + PCI_ACS_CTRL, cap_bits); in pcie_acs_init()
1211 void pcie_acs_reset(PCIDevice *dev) in pcie_acs_reset() argument
1213 if (dev->exp.acs_cap) { in pcie_acs_reset()
1214 pci_set_word(dev->config + dev->exp.acs_cap + PCI_ACS_CTRL, 0); in pcie_acs_reset()
1219 void pcie_pasid_init(PCIDevice *dev, uint16_t offset, uint8_t pasid_width, in pcie_pasid_init() argument
1222 static const uint16_t control_reg_rw_mask = 0x07; in pcie_pasid_init()
1227 pcie_add_capability(dev, PCI_EXT_CAP_ID_PASID, PCI_PASID_VER, offset, in pcie_pasid_init()
1231 capability_reg |= exec_perm ? PCI_PASID_CAP_EXEC : 0; in pcie_pasid_init()
1232 capability_reg |= priv_mod ? PCI_PASID_CAP_PRIV : 0; in pcie_pasid_init()
1233 pci_set_word(dev->config + offset + PCI_PASID_CAP, capability_reg); in pcie_pasid_init()
1236 pci_set_word(dev->config + offset + PCI_PASID_CTRL, 0); in pcie_pasid_init()
1238 pci_set_word(dev->wmask + offset + PCI_PASID_CTRL, control_reg_rw_mask); in pcie_pasid_init()
1240 dev->exp.pasid_cap = offset; in pcie_pasid_init()
1244 void pcie_pri_init(PCIDevice *dev, uint16_t offset, uint32_t outstanding_pr_cap, in pcie_pri_init() argument
1247 static const uint16_t control_reg_rw_mask = 0x3; in pcie_pri_init()
1248 static const uint16_t status_reg_rw1_mask = 0x3; in pcie_pri_init()
1249 static const uint32_t pr_alloc_reg_rw_mask = 0xffffffff; in pcie_pri_init()
1252 status_reg = prg_response_pasid_req ? PCI_PRI_STATUS_PASID : 0; in pcie_pri_init()
1255 pcie_add_capability(dev, PCI_EXT_CAP_ID_PRI, PCI_PRI_VER, offset, in pcie_pri_init()
1259 pci_set_word(dev->config + offset + PCI_PRI_STATUS, status_reg); in pcie_pri_init()
1260 pci_set_long(dev->config + offset + PCI_PRI_MAX_REQ, outstanding_pr_cap); in pcie_pri_init()
1262 pci_set_word(dev->wmask + offset + PCI_PRI_CTRL, control_reg_rw_mask); in pcie_pri_init()
1263 pci_set_word(dev->w1cmask + offset + PCI_PRI_STATUS, status_reg_rw1_mask); in pcie_pri_init()
1264 pci_set_long(dev->wmask + offset + PCI_PRI_ALLOC_REQ, pr_alloc_reg_rw_mask); in pcie_pri_init()
1266 dev->exp.pri_cap = offset; in pcie_pri_init()
1269 bool pcie_pri_enabled(const PCIDevice *dev) in pcie_pri_enabled() argument
1271 if (!pci_is_express(dev) || !dev->exp.pri_cap) { in pcie_pri_enabled()
1274 return (pci_get_word(dev->config + dev->exp.pri_cap + PCI_PRI_CTRL) & in pcie_pri_enabled()
1275 PCI_PRI_CTRL_ENABLE) != 0; in pcie_pri_enabled()
1278 bool pcie_pasid_enabled(const PCIDevice *dev) in pcie_pasid_enabled() argument
1280 if (!pci_is_express(dev) || !dev->exp.pasid_cap) { in pcie_pasid_enabled()
1283 return (pci_get_word(dev->config + dev->exp.pasid_cap + PCI_PASID_CTRL) & in pcie_pasid_enabled()
1284 PCI_PASID_CTRL_ENABLE) != 0; in pcie_pasid_enabled()
1287 bool pcie_ats_enabled(const PCIDevice *dev) in pcie_ats_enabled() argument
1289 if (!pci_is_express(dev) || !dev->exp.ats_cap) { in pcie_ats_enabled()
1292 return (pci_get_word(dev->config + dev->exp.ats_cap + PCI_ATS_CTRL) & in pcie_ats_enabled()
1293 PCI_ATS_CTRL_ENABLE) != 0; in pcie_ats_enabled()