Lines Matching +full:check +full:- +full:patch
33 #include "hw/qdev-properties.h"
34 #include "hw/qdev-properties-system.h"
36 #include "migration/qemu-file-types.h"
43 #include "qemu/error-report.h"
53 #include "pci-internal.h"
79 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1),
82 DEFINE_PROP_INT32("rombar", PCIDevice, rom_bar, -1),
85 DEFINE_PROP_BIT("x-pcie-lnksta-dllla", PCIDevice, cap_present,
87 DEFINE_PROP_BIT("x-pcie-extcap-init", PCIDevice, cap_present,
91 DEFINE_PROP_UINT32("acpi-index", PCIDevice, acpi_index, 0),
92 DEFINE_PROP_BIT("x-pcie-err-unc-mask", PCIDevice, cap_present,
94 DEFINE_PROP_BIT("x-pcie-ari-nextfn-1", PCIDevice, cap_present,
96 DEFINE_PROP_SIZE32("x-max-bounce-buffer-size", PCIDevice,
98 DEFINE_PROP_STRING("sriov-pf", PCIDevice, sriov_pf),
99 DEFINE_PROP_BIT("x-pcie-ext-tag", PCIDevice, cap_present,
119 return a - b; in g_cmp_uint32()
134 memory_region_set_enabled(&d->bus_master_enable_region, enable); in pci_set_master()
135 d->is_master = enable; /* cache the status */ in pci_set_master()
142 memory_region_init_alias(&pci_dev->bus_master_enable_region, in pci_init_bus_master()
144 dma_as->root, 0, memory_region_size(dma_as->root)); in pci_init_bus_master()
146 memory_region_add_subregion(&pci_dev->bus_master_container_region, 0, in pci_init_bus_master()
147 &pci_dev->bus_master_enable_region); in pci_init_bus_master()
155 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { in pcibus_machine_done()
156 if (bus->devices[i]) { in pcibus_machine_done()
157 pci_init_bus_master(bus->devices[i]); in pcibus_machine_done()
166 bus->machine_done.notify = pcibus_machine_done; in pci_bus_realize()
167 qemu_add_machine_init_done_notifier(&bus->machine_done); in pci_bus_realize()
184 * A PCI-E bus can support extended config space if it's the root in pcie_bus_realize()
188 bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE; in pcie_bus_realize()
190 PCIBus *parent_bus = pci_get_bus(bus->parent_dev); in pcie_bus_realize()
193 bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE; in pcie_bus_realize()
202 qemu_remove_machine_init_done_notifier(&bus->machine_done); in pci_bus_unrealize()
212 return bus->parent_dev->config[PCI_SECONDARY_BUS]; in pcibus_num()
231 return fw_cfg_add_file_from_generator(fw_cfg, obj->parent, in pci_bus_add_fw_cfg_extra_pci_roots()
233 "etc/extra-pci-roots", errp); in pci_bus_add_fw_cfg_extra_pci_roots()
246 QLIST_FOREACH(bus, &bus->child, sibling) { in pci_bus_fw_cfg_gen_data()
272 k->print_dev = pcibus_dev_print; in pci_bus_class_init()
273 k->get_dev_path = pcibus_get_dev_path; in pci_bus_class_init()
274 k->get_fw_dev_path = pcibus_get_fw_dev_path; in pci_bus_class_init()
275 k->realize = pci_bus_realize; in pci_bus_class_init()
276 k->unrealize = pci_bus_unrealize; in pci_bus_class_init()
278 rc->phases.hold = pcibus_reset_hold; in pci_bus_class_init()
280 pbc->bus_num = pcibus_num; in pci_bus_class_init()
281 pbc->numa_node = pcibus_numa_node; in pci_bus_class_init()
283 fwgc->get_data = pci_bus_fw_cfg_gen_data; in pci_bus_class_init()
317 k->realize = pcie_bus_realize; in pcie_bus_class_init()
352 type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; in pci_bar()
358 return (d->irq_state >> irq_num) & 0x1; in pci_irq_state()
363 d->irq_state &= ~(0x1 << irq_num); in pci_set_irq_state()
364 d->irq_state |= level << irq_num; in pci_set_irq_state()
370 assert(irq_num < bus->nirq); in pci_bus_change_irq_level()
371 bus->irq_count[irq_num] += change; in pci_bus_change_irq_level()
372 bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0); in pci_bus_change_irq_level()
381 assert(bus->map_irq); in pci_change_irq_level()
382 irq_num = bus->map_irq(pci_dev, irq_num); in pci_change_irq_level()
383 trace_pci_route_irq(dev_irq, DEVICE(pci_dev)->canonical_path, irq_num, in pci_change_irq_level()
384 pci_bus_is_root(bus) ? "root-complex" in pci_change_irq_level()
385 : DEVICE(bus->parent_dev)->canonical_path); in pci_change_irq_level()
386 if (bus->set_irq) in pci_change_irq_level()
388 pci_dev = bus->parent_dev; in pci_change_irq_level()
396 assert(irq_num < bus->nirq); in pci_bus_get_irq_level()
397 return !!bus->irq_count[irq_num]; in pci_bus_get_irq_level()
404 if (dev->irq_state) { in pci_update_irq_status()
405 dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT; in pci_update_irq_status()
407 dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT; in pci_update_irq_status()
435 address_space_stl_le(&dev->bus_master_as, msg.address, msg.data, in pci_msi_trigger()
453 d->pm_cap = cap; in pci_pm_init()
454 d->cap_present |= QEMU_PCI_CAP_PM; in pci_pm_init()
463 if (!(d->cap_present & QEMU_PCI_CAP_PM)) { in pci_pm_state()
467 pmcsr = pci_get_word(d->config + d->pm_cap + PCI_PM_CTRL); in pci_pm_state()
474 * space respective to the old, pre-write state provided. If the new value
483 if (!(d->cap_present & QEMU_PCI_CAP_PM) || in pci_pm_update()
484 !range_covers_byte(addr, l, d->pm_cap + PCI_PM_CTRL)) { in pci_pm_update()
493 pmc = pci_get_word(d->config + d->pm_cap + PCI_PM_PMC); in pci_pm_update()
497 * only transition to higher D-states or to D0. in pci_pm_update()
502 pci_word_test_and_clear_mask(d->config + d->pm_cap + PCI_PM_CTRL, in pci_pm_update()
504 pci_word_test_and_set_mask(d->config + d->pm_cap + PCI_PM_CTRL, in pci_pm_update()
506 trace_pci_pm_bad_transition(d->name, pci_dev_bus_num(d), in pci_pm_update()
507 PCI_SLOT(d->devfn), PCI_FUNC(d->devfn), in pci_pm_update()
512 trace_pci_pm_transition(d->name, pci_dev_bus_num(d), PCI_SLOT(d->devfn), in pci_pm_update()
513 PCI_FUNC(d->devfn), old, new); in pci_pm_update()
525 PCIIORegion *region = &dev->io_regions[r]; in pci_reset_regions()
526 if (!region->size) { in pci_reset_regions()
530 if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) && in pci_reset_regions()
531 region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) { in pci_reset_regions()
532 pci_set_quad(dev->config + pci_bar(dev, r), region->type); in pci_reset_regions()
534 pci_set_long(dev->config + pci_bar(dev, r), region->type); in pci_reset_regions()
541 if ((dev->cap_present & QEMU_PCI_SKIP_RESET_ON_CPR) && cpr_is_incoming()) { in pci_do_device_reset()
546 assert(dev->irq_state == 0); in pci_do_device_reset()
549 pci_word_test_and_clear_mask(dev->config + PCI_COMMAND, in pci_do_device_reset()
550 pci_get_word(dev->wmask + PCI_COMMAND) | in pci_do_device_reset()
551 pci_get_word(dev->w1cmask + PCI_COMMAND)); in pci_do_device_reset()
552 pci_word_test_and_clear_mask(dev->config + PCI_STATUS, in pci_do_device_reset()
553 pci_get_word(dev->wmask + PCI_STATUS) | in pci_do_device_reset()
554 pci_get_word(dev->w1cmask + PCI_STATUS)); in pci_do_device_reset()
556 pci_byte_test_and_clear_mask(dev->config + PCI_INTERRUPT_LINE, in pci_do_device_reset()
557 pci_get_word(dev->wmask + PCI_INTERRUPT_LINE) | in pci_do_device_reset()
558 pci_get_word(dev->w1cmask + PCI_INTERRUPT_LINE)); in pci_do_device_reset()
559 dev->config[PCI_CACHE_LINE_SIZE] = 0x0; in pci_do_device_reset()
561 if (dev->cap_present & QEMU_PCI_CAP_PM) { in pci_do_device_reset()
562 pci_word_test_and_clear_mask(dev->config + dev->pm_cap + PCI_PM_CTRL, in pci_do_device_reset()
579 device_cold_reset(&dev->qdev); in pci_device_reset()
586 * have been reset device_cold_reset-ed already.
593 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { in pcibus_reset_hold()
594 if (bus->devices[i]) { in pcibus_reset_hold()
595 pci_do_device_reset(bus->devices[i]); in pcibus_reset_hold()
599 for (i = 0; i < bus->nirq; i++) { in pcibus_reset_hold()
600 assert(bus->irq_count[i] == 0); in pcibus_reset_hold()
623 d = bus->parent_dev; in pci_device_root_bus()
635 PCIHostState *host_bridge = PCI_HOST_BRIDGE(rootbus->qbus.parent); in pci_root_bus_path()
638 assert(host_bridge->bus == rootbus); in pci_root_bus_path()
640 if (hc->root_bus_path) { in pci_root_bus_path()
641 return (*hc->root_bus_path)(host_bridge, rootbus); in pci_root_bus_path()
644 return rootbus->qbus.name; in pci_root_bus_path()
653 rootbus = pci_device_root_bus(bus->parent_dev); in pci_bus_bypass_iommu()
656 host_bridge = PCI_HOST_BRIDGE(rootbus->qbus.parent); in pci_bus_bypass_iommu()
658 assert(host_bridge->bus == rootbus); in pci_bus_bypass_iommu()
660 return host_bridge->bypass_iommu; in pci_bus_bypass_iommu()
668 bus->devfn_min = devfn_min; in pci_root_bus_internal_init()
669 bus->slot_reserved_mask = 0x0; in pci_root_bus_internal_init()
670 bus->address_space_mem = mem; in pci_root_bus_internal_init()
671 bus->address_space_io = io; in pci_root_bus_internal_init()
672 bus->flags |= PCI_BUS_IS_ROOT; in pci_root_bus_internal_init()
675 QLIST_INIT(&bus->child); in pci_root_bus_internal_init()
682 pci_host_bus_unregister(BUS(bus)->parent); in pci_bus_uninit()
720 bus->set_irq = set_irq; in pci_bus_irqs()
721 bus->irq_opaque = irq_opaque; in pci_bus_irqs()
722 bus->nirq = nirq; in pci_bus_irqs()
723 g_free(bus->irq_count); in pci_bus_irqs()
724 bus->irq_count = g_malloc0(nirq * sizeof(bus->irq_count[0])); in pci_bus_irqs()
729 bus->map_irq = map_irq; in pci_bus_map_irqs()
734 bus->set_irq = NULL; in pci_bus_irqs_cleanup()
735 bus->map_irq = NULL; in pci_bus_irqs_cleanup()
736 bus->irq_opaque = NULL; in pci_bus_irqs_cleanup()
737 bus->nirq = 0; in pci_bus_irqs_cleanup()
738 g_free(bus->irq_count); in pci_bus_irqs_cleanup()
739 bus->irq_count = NULL; in pci_bus_irqs_cleanup()
765 return PCI_BUS_GET_CLASS(s)->bus_num(s); in pci_bus_num()
774 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { in pci_bus_range()
775 PCIDevice *dev = bus->devices[i]; in pci_bus_range()
778 *min_bus = MIN(*min_bus, dev->config[PCI_SECONDARY_BUS]); in pci_bus_range()
779 *max_bus = MAX(*max_bus, dev->config[PCI_SUBORDINATE_BUS]); in pci_bus_range()
786 return PCI_BUS_GET_CLASS(bus)->numa_node(bus); in pci_bus_numa_node()
801 if ((config[i] ^ s->config[i]) & in get_pci_config_device()
802 s->cmask[i] & ~s->wmask[i] & ~s->w1cmask[i]) { in get_pci_config_device()
805 i, config[i], s->config[i], in get_pci_config_device()
806 s->cmask[i], s->wmask[i], s->w1cmask[i]); in get_pci_config_device()
808 return -EINVAL; in get_pci_config_device()
811 memcpy(s->config, config, size); in get_pci_config_device()
818 pci_set_master(s, pci_get_word(s->config + PCI_COMMAND) in get_pci_config_device()
853 return -EINVAL; in get_pci_irq_state()
928 s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT; in pci_device_save()
937 ret = vmstate_load_state(f, &vmstate_pci_device, s, s->version_id); in pci_device_load()
945 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, in pci_set_default_subsystem_id()
947 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, in pci_set_default_subsystem_id()
952 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL
953 * [[<domain>:]<bus>:]<slot>.<func>, return -1 on error
968 return -1; in pci_parse_devaddr()
974 return -1; in pci_parse_devaddr()
981 return -1; in pci_parse_devaddr()
989 return -1; in pci_parse_devaddr()
994 return -1; in pci_parse_devaddr()
1001 return -1; in pci_parse_devaddr()
1004 return -1; in pci_parse_devaddr()
1016 pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff); in pci_init_cmask()
1017 pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff); in pci_init_cmask()
1018 dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST; in pci_init_cmask()
1019 dev->cmask[PCI_REVISION_ID] = 0xff; in pci_init_cmask()
1020 dev->cmask[PCI_CLASS_PROG] = 0xff; in pci_init_cmask()
1021 pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff); in pci_init_cmask()
1022 dev->cmask[PCI_HEADER_TYPE] = 0xff; in pci_init_cmask()
1023 dev->cmask[PCI_CAPABILITY_LIST] = 0xff; in pci_init_cmask()
1030 dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff; in pci_init_wmask()
1031 dev->wmask[PCI_INTERRUPT_LINE] = 0xff; in pci_init_wmask()
1032 pci_set_word(dev->wmask + PCI_COMMAND, in pci_init_wmask()
1035 pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND, PCI_COMMAND_SERR); in pci_init_wmask()
1037 memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff, in pci_init_wmask()
1038 config_size - PCI_CONFIG_HEADER_SIZE); in pci_init_wmask()
1047 pci_set_word(dev->w1cmask + PCI_STATUS, in pci_init_w1cmask()
1057 memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4); in pci_init_mask_bridge()
1060 d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff; in pci_init_mask_bridge()
1061 d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff; in pci_init_mask_bridge()
1062 pci_set_word(d->wmask + PCI_MEMORY_BASE, in pci_init_mask_bridge()
1064 pci_set_word(d->wmask + PCI_MEMORY_LIMIT, in pci_init_mask_bridge()
1066 pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE, in pci_init_mask_bridge()
1068 pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT, in pci_init_mask_bridge()
1072 memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8); in pci_init_mask_bridge()
1075 d->config[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_16; in pci_init_mask_bridge()
1076 d->config[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_16; in pci_init_mask_bridge()
1077 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_BASE, in pci_init_mask_bridge()
1079 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_LIMIT, in pci_init_mask_bridge()
1083 * TODO: Bridges default to 10-bit VGA decoding but we currently only in pci_init_mask_bridge()
1084 * implement 16-bit decoding (no alias support). in pci_init_mask_bridge()
1086 pci_set_word(d->wmask + PCI_BRIDGE_CONTROL, in pci_init_mask_bridge()
1100 pci_set_word(d->w1cmask + PCI_BRIDGE_CONTROL, in pci_init_mask_bridge()
1102 d->cmask[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_MASK; in pci_init_mask_bridge()
1103 d->cmask[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_MASK; in pci_init_mask_bridge()
1104 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_BASE, in pci_init_mask_bridge()
1106 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_LIMIT, in pci_init_mask_bridge()
1112 uint8_t slot = PCI_SLOT(dev->devfn); in pci_init_multifunction()
1115 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) { in pci_init_multifunction()
1116 dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION; in pci_init_multifunction()
1126 * - all functions must set the bit to 1. in pci_init_multifunction()
1128 * - function 0 must set the bit, but the rest function (> 0) in pci_init_multifunction()
1135 * The below check allows both interpretation. in pci_init_multifunction()
1137 if (PCI_FUNC(dev->devfn)) { in pci_init_multifunction()
1138 PCIDevice *f0 = bus->devices[PCI_DEVFN(slot, 0)]; in pci_init_multifunction()
1139 if (f0 && !(f0->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)) { in pci_init_multifunction()
1142 "in function %x.%x", slot, PCI_FUNC(dev->devfn)); in pci_init_multifunction()
1148 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) { in pci_init_multifunction()
1153 PCIDevice *device = bus->devices[PCI_DEVFN(slot, func)]; in pci_init_multifunction()
1167 pci_dev->config = g_malloc0(config_size); in pci_config_alloc()
1168 pci_dev->cmask = g_malloc0(config_size); in pci_config_alloc()
1169 pci_dev->wmask = g_malloc0(config_size); in pci_config_alloc()
1170 pci_dev->w1cmask = g_malloc0(config_size); in pci_config_alloc()
1171 pci_dev->used = g_malloc0(config_size); in pci_config_alloc()
1176 g_free(pci_dev->config); in pci_config_free()
1177 g_free(pci_dev->cmask); in pci_config_free()
1178 g_free(pci_dev->wmask); in pci_config_free()
1179 g_free(pci_dev->w1cmask); in pci_config_free()
1180 g_free(pci_dev->used); in pci_config_free()
1185 pci_get_bus(pci_dev)->devices[pci_dev->devfn] = NULL; in do_pci_unregister_device()
1191 if (memory_region_is_mapped(&pci_dev->bus_master_enable_region)) { in do_pci_unregister_device()
1192 memory_region_del_subregion(&pci_dev->bus_master_container_region, in do_pci_unregister_device()
1193 &pci_dev->bus_master_enable_region); in do_pci_unregister_device()
1195 address_space_destroy(&pci_dev->bus_master_as); in do_pci_unregister_device()
1204 switch (cache->type) { in pci_req_id_cache_extract()
1206 result = pci_get_bdf(cache->dev); in pci_req_id_cache_extract()
1209 bus_n = pci_dev_bus_num(cache->dev); in pci_req_id_cache_extract()
1214 cache->type); in pci_req_id_cache_extract()
1226 * legacy PCI devices and PCIe-to-PCI bridges.
1241 parent = pci_get_bus(dev)->parent_dev; in pci_req_id_cache_get()
1244 /* When we pass through PCIe-to-PCI/PCIX bridges, we in pci_req_id_cache_get()
1247 * (pcie-to-pci bridge spec chap 2.3). */ in pci_req_id_cache_get()
1270 return pci_req_id_cache_extract(&dev->requester_id_cache); in pci_requester_id()
1275 return !(bus->devices[devfn]); in pci_bus_devfn_available()
1280 return bus->slot_reserved_mask & (1UL << PCI_SLOT(devfn)); in pci_bus_devfn_reserved()
1285 return bus->slot_reserved_mask; in pci_bus_get_slot_reserved_mask()
1290 bus->slot_reserved_mask |= mask; in pci_bus_set_slot_reserved_mask()
1295 bus->slot_reserved_mask &= ~mask; in pci_bus_clear_slot_reserved_mask()
1298 /* -1 for devfn means auto assign */
1304 PCIConfigReadFunc *config_read = pc->config_read; in do_pci_register_device()
1305 PCIConfigWriteFunc *config_write = pc->config_write; in do_pci_register_device()
1312 if (pci_bus_is_root(bus) && bus->parent_dev && !is_bridge) { in do_pci_register_device()
1315 bus->parent_dev->name); in do_pci_register_device()
1320 for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices); in do_pci_register_device()
1340 bus->devices[devfn]->name, bus->devices[devfn]->qdev.id); in do_pci_register_device()
1346 * exposes other non-zero functions. Hence we need to ensure that in do_pci_register_device()
1349 if (dev->hotplugged && !pci_is_vf(pci_dev) && in do_pci_register_device()
1353 PCI_SLOT(pci_get_function_0(pci_dev)->devfn), in do_pci_register_device()
1354 pci_get_function_0(pci_dev)->name, in do_pci_register_device()
1360 pci_dev->devfn = devfn; in do_pci_register_device()
1361 pci_dev->requester_id_cache = pci_req_id_cache_get(pci_dev); in do_pci_register_device()
1362 pstrcpy(pci_dev->name, sizeof(pci_dev->name), name); in do_pci_register_device()
1364 memory_region_init(&pci_dev->bus_master_container_region, OBJECT(pci_dev), in do_pci_register_device()
1366 address_space_init(&pci_dev->bus_master_as, in do_pci_register_device()
1367 &pci_dev->bus_master_container_region, pci_dev->name); in do_pci_register_device()
1368 pci_dev->bus_master_as.max_bounce_buffer_size = in do_pci_register_device()
1369 pci_dev->max_bounce_buffer_size; in do_pci_register_device()
1374 pci_dev->irq_state = 0; in do_pci_register_device()
1377 pci_config_set_vendor_id(pci_dev->config, pc->vendor_id); in do_pci_register_device()
1378 pci_config_set_device_id(pci_dev->config, pc->device_id); in do_pci_register_device()
1379 pci_config_set_revision(pci_dev->config, pc->revision); in do_pci_register_device()
1380 pci_config_set_class(pci_dev->config, pc->class_id); in do_pci_register_device()
1383 if (pc->subsystem_vendor_id || pc->subsystem_id) { in do_pci_register_device()
1384 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, in do_pci_register_device()
1385 pc->subsystem_vendor_id); in do_pci_register_device()
1386 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, in do_pci_register_device()
1387 pc->subsystem_id); in do_pci_register_device()
1393 assert(!pc->subsystem_vendor_id); in do_pci_register_device()
1394 assert(!pc->subsystem_id); in do_pci_register_device()
1413 pci_dev->config_read = config_read; in do_pci_register_device()
1414 pci_dev->config_write = config_write; in do_pci_register_device()
1415 bus->devices[devfn] = pci_dev; in do_pci_register_device()
1416 pci_dev->version_id = 2; /* Current pci device vmstate version */ in do_pci_register_device()
1426 r = &pci_dev->io_regions[i]; in pci_unregister_io_regions()
1427 if (!r->size || r->addr == PCI_BAR_UNMAPPED) in pci_unregister_io_regions()
1429 memory_region_del_subregion(r->address_space, r->memory); in pci_unregister_io_regions()
1444 if (pc->exit) { in pci_qdev_unrealize()
1445 pc->exit(pci_dev); in pci_qdev_unrealize()
1451 pci_dev->msi_trigger = NULL; in pci_qdev_unrealize()
1454 * clean up acpi-index so it could reused by another device in pci_qdev_unrealize()
1456 if (pci_dev->acpi_index) { in pci_qdev_unrealize()
1460 GINT_TO_POINTER(pci_dev->acpi_index), in pci_qdev_unrealize()
1480 pci_dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; in pci_register_bar()
1483 r = &pci_dev->io_regions[region_num]; in pci_register_bar()
1484 assert(!r->size); in pci_register_bar()
1485 r->size = size; in pci_register_bar()
1486 r->type = type; in pci_register_bar()
1487 r->memory = memory; in pci_register_bar()
1488 r->address_space = type & PCI_BASE_ADDRESS_SPACE_IO in pci_register_bar()
1489 ? pci_get_bus(pci_dev)->address_space_io in pci_register_bar()
1490 : pci_get_bus(pci_dev)->address_space_mem; in pci_register_bar()
1493 PCIDevice *pf = pci_dev->exp.sriov_vf.pf; in pci_register_bar()
1494 assert(!pf || type == pf->exp.sriov_pf.vf_bar_type[region_num]); in pci_register_bar()
1496 r->addr = pci_bar_address(pci_dev, region_num, r->type, r->size); in pci_register_bar()
1497 if (r->addr != PCI_BAR_UNMAPPED) { in pci_register_bar()
1498 memory_region_add_subregion_overlap(r->address_space, in pci_register_bar()
1499 r->addr, r->memory, 1); in pci_register_bar()
1502 r->addr = PCI_BAR_UNMAPPED; in pci_register_bar()
1504 wmask = ~(size - 1); in pci_register_bar()
1511 pci_set_long(pci_dev->config + addr, type); in pci_register_bar()
1513 if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) && in pci_register_bar()
1514 r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) { in pci_register_bar()
1515 pci_set_quad(pci_dev->wmask + addr, wmask); in pci_register_bar()
1516 pci_set_quad(pci_dev->cmask + addr, ~0ULL); in pci_register_bar()
1518 pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff); in pci_register_bar()
1519 pci_set_long(pci_dev->cmask + addr, 0xffffffff); in pci_register_bar()
1528 if (!pci_dev->has_vga) { in pci_update_vga()
1532 cmd = pci_get_word(pci_dev->config + PCI_COMMAND); in pci_update_vga()
1534 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_MEM], in pci_update_vga()
1536 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO], in pci_update_vga()
1538 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI], in pci_update_vga()
1547 assert(!pci_dev->has_vga); in pci_register_vga()
1550 pci_dev->vga_regions[QEMU_PCI_VGA_MEM] = mem; in pci_register_vga()
1551 memory_region_add_subregion_overlap(bus->address_space_mem, in pci_register_vga()
1555 pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO] = io_lo; in pci_register_vga()
1556 memory_region_add_subregion_overlap(bus->address_space_io, in pci_register_vga()
1560 pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI] = io_hi; in pci_register_vga()
1561 memory_region_add_subregion_overlap(bus->address_space_io, in pci_register_vga()
1563 pci_dev->has_vga = true; in pci_register_vga()
1572 if (!pci_dev->has_vga) { in pci_unregister_vga()
1576 memory_region_del_subregion(bus->address_space_mem, in pci_unregister_vga()
1577 pci_dev->vga_regions[QEMU_PCI_VGA_MEM]); in pci_unregister_vga()
1578 memory_region_del_subregion(bus->address_space_io, in pci_unregister_vga()
1579 pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO]); in pci_unregister_vga()
1580 memory_region_del_subregion(bus->address_space_io, in pci_unregister_vga()
1581 pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI]); in pci_unregister_vga()
1582 pci_dev->has_vga = false; in pci_unregister_vga()
1587 return pci_dev->io_regions[region_num].addr; in pci_get_bar_addr()
1597 new_addr = pci_get_quad(d->config + bar); in pci_config_get_bar_addr()
1599 new_addr = pci_get_long(d->config + bar); in pci_config_get_bar_addr()
1602 PCIDevice *pf = d->exp.sriov_vf.pf; in pci_config_get_bar_addr()
1603 uint16_t sriov_cap = pf->exp.sriov_cap; in pci_config_get_bar_addr()
1606 pci_get_word(pf->config + sriov_cap + PCI_SRIOV_VF_OFFSET); in pci_config_get_bar_addr()
1608 pci_get_word(pf->config + sriov_cap + PCI_SRIOV_VF_STRIDE); in pci_config_get_bar_addr()
1609 uint32_t vf_num = d->devfn - (pf->devfn + vf_offset); in pci_config_get_bar_addr()
1616 new_addr = pci_get_quad(pf->config + bar); in pci_config_get_bar_addr()
1618 new_addr = pci_get_long(pf->config + bar); in pci_config_get_bar_addr()
1624 new_addr &= ~(size - 1); in pci_config_get_bar_addr()
1633 uint16_t cmd = pci_get_word(d->config + PCI_COMMAND); in pci_bar_address()
1635 bool allow_0_address = mc->pci_allow_0_address; in pci_bar_address()
1642 last_addr = new_addr + size - 1; in pci_bar_address()
1643 /* Check if 32 bit BAR wraps around explicitly. in pci_bar_address()
1661 new_addr &= ~(size - 1); in pci_bar_address()
1662 last_addr = new_addr + size - 1; in pci_bar_address()
1673 * Check if 32 bit BAR wraps around explicitly. in pci_bar_address()
1684 * to >4G. Check it. TODO: we might need to support in pci_bar_address()
1701 r = &d->io_regions[i]; in pci_update_mappings()
1704 if (!r->size) in pci_update_mappings()
1707 new_addr = pci_bar_address(d, i, r->type, r->size); in pci_update_mappings()
1708 if (!d->enabled || pci_pm_state(d)) { in pci_update_mappings()
1713 if (new_addr == r->addr) in pci_update_mappings()
1717 if (r->addr != PCI_BAR_UNMAPPED) { in pci_update_mappings()
1718 trace_pci_update_mappings_del(d->name, pci_dev_bus_num(d), in pci_update_mappings()
1719 PCI_SLOT(d->devfn), in pci_update_mappings()
1720 PCI_FUNC(d->devfn), in pci_update_mappings()
1721 i, r->addr, r->size); in pci_update_mappings()
1722 memory_region_del_subregion(r->address_space, r->memory); in pci_update_mappings()
1724 r->addr = new_addr; in pci_update_mappings()
1725 if (r->addr != PCI_BAR_UNMAPPED) { in pci_update_mappings()
1726 trace_pci_update_mappings_add(d->name, pci_dev_bus_num(d), in pci_update_mappings()
1727 PCI_SLOT(d->devfn), in pci_update_mappings()
1728 PCI_FUNC(d->devfn), in pci_update_mappings()
1729 i, r->addr, r->size); in pci_update_mappings()
1730 memory_region_add_subregion_overlap(r->address_space, in pci_update_mappings()
1731 r->addr, r->memory, 1); in pci_update_mappings()
1740 return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE; in pci_irq_disabled()
1753 pci_change_irq_level(d, i, disabled ? -state : state); in pci_update_irq_disabled()
1765 ranges_overlap(address, len, d->exp.exp_cap + PCI_EXP_LNKSTA, 2)) { in pci_default_read_config()
1768 memcpy(&val, d->config + address, len); in pci_default_read_config()
1781 uint8_t wmask = d->wmask[addr + i]; in pci_default_write_config()
1782 uint8_t w1cmask = d->w1cmask[addr + i]; in pci_default_write_config()
1784 d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask); in pci_default_write_config()
1785 d->config[addr + i] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */ in pci_default_write_config()
1800 pci_set_master(d, (pci_get_word(d->config + PCI_COMMAND) & in pci_default_write_config()
1801 PCI_COMMAND_MASTER) && d->enabled); in pci_default_write_config()
1820 change = level - pci_irq_state(pci_dev, irq_num); in pci_irq_handler()
1849 bus->route_intx_to_irq = route_intx_to_irq; in pci_bus_set_route_irq_fn()
1859 pin = bus->map_irq(dev, pin); in pci_device_route_intx_to_irq()
1860 trace_pci_route_irq(dev_irq, DEVICE(dev)->canonical_path, pin, in pci_device_route_intx_to_irq()
1861 pci_bus_is_root(bus) ? "root-complex" in pci_device_route_intx_to_irq()
1862 : DEVICE(bus->parent_dev)->canonical_path); in pci_device_route_intx_to_irq()
1863 dev = bus->parent_dev; in pci_device_route_intx_to_irq()
1866 if (!bus->route_intx_to_irq) { in pci_device_route_intx_to_irq()
1867 error_report("PCI: Bug - unimplemented PCI INTx routing (%s)", in pci_device_route_intx_to_irq()
1868 object_get_typename(OBJECT(bus->qbus.parent))); in pci_device_route_intx_to_irq()
1869 return (PCIINTxRoute) { PCI_INTX_DISABLED, -1 }; in pci_device_route_intx_to_irq()
1872 return bus->route_intx_to_irq(bus->irq_opaque, pin); in pci_device_route_intx_to_irq()
1877 return old->mode != new->mode || old->irq != new->irq; in pci_intx_route_changed()
1886 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { in pci_bus_fire_intx_routing_notifier()
1887 dev = bus->devices[i]; in pci_bus_fire_intx_routing_notifier()
1888 if (dev && dev->intx_routing_notifier) { in pci_bus_fire_intx_routing_notifier()
1889 dev->intx_routing_notifier(dev); in pci_bus_fire_intx_routing_notifier()
1893 QLIST_FOREACH(sec, &bus->child, sibling) { in pci_bus_fire_intx_routing_notifier()
1901 dev->intx_routing_notifier = notifier; in pci_device_set_intx_routing_notifier()
1905 * PCI-to-PCI bridge specification
1906 * 9.1: Interrupt routing. Table 9-1
1909 * 2.2.8.1: INTx interrupt signaling - Rules
1911 * Table 2-20
1915 * 0-origin unlike PCI interrupt pin register.
1919 return pci_swizzle(PCI_SLOT(pci_dev->devfn), pin); in pci_swizzle_map_irq_fn()
1937 { 0x0201, "Token Ring controller", "token-ring"},
1957 { 0x0604, "PCI bridge", "pci-bridge"},
1965 { 0x0800, "Interrupt controller", "interrupt-controller"},
1966 { 0x0801, "DMA controller", "dma-controller"},
1975 { 0x0c01, "Access bus controller", "access-bus"},
1978 { 0x0c04, "Fibre channel controller", "fibre-channel"},
1990 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { in pci_for_each_device_under_bus_reverse()
1991 d = bus->devices[ARRAY_SIZE(bus->devices) - 1 - devfn]; in pci_for_each_device_under_bus_reverse()
2014 for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { in pci_for_each_device_under_bus()
2015 d = bus->devices[devfn]; in pci_for_each_device_under_bus()
2037 while (desc->desc && class != desc->class) { in get_class_desc()
2046 qemu_create_nic_bus_devices(&bus->qbus, TYPE_PCI_DEVICE, default_model, in pci_init_nic_devices()
2047 "virtio", "virtio-net-pci"); in pci_init_nic_devices()
2070 error_report("No support for non-zero PCI domains"); in pci_init_nic_in_slot()
2084 qdev_set_nic_properties(&pci_dev->qdev, nd); in pci_init_nic_in_slot()
2094 return pci_create_simple(bus, -1, "cirrus-vga"); in pci_vga_init()
2096 return pci_create_simple(bus, -1, "qxl-vga"); in pci_vga_init()
2098 return pci_create_simple(bus, -1, "VGA"); in pci_vga_init()
2100 return pci_create_simple(bus, -1, "vmware-svga"); in pci_vga_init()
2102 return pci_create_simple(bus, -1, "virtio-vga"); in pci_vga_init()
2104 default: /* Other non-PCI types. Checking for unsupported types is already in pci_vga_init()
2114 return !(pci_get_word(dev->config + PCI_BRIDGE_CONTROL) & in pci_secondary_bus_in_range()
2116 dev->config[PCI_SECONDARY_BUS] <= bus_num && in pci_secondary_bus_in_range()
2117 bus_num <= dev->config[PCI_SUBORDINATE_BUS]; in pci_secondary_bus_in_range()
2125 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { in pci_root_bus_in_range()
2126 PCIDevice *dev = bus->devices[i]; in pci_root_bus_in_range()
2152 !pci_secondary_bus_in_range(bus->parent_dev, bus_num)) { in pci_find_bus_nr()
2158 QLIST_FOREACH(sec, &bus->child, sibling) { in pci_find_bus_nr()
2168 if (pci_secondary_bus_in_range(sec->parent_dev, bus_num)) { in pci_find_bus_nr()
2194 QLIST_FOREACH(sec, &bus->child, sibling) { in pci_for_each_bus_depth_first()
2211 return bus->devices[devfn]; in pci_find_device()
2214 #define ONBOARD_INDEX_MAX (16 * 1024 - 1)
2226 * capped by systemd (see: udev-builtin-net_id.c) in pci_qdev_realize()
2228 * misconfigure QEMU and then wonder why acpi-index doesn't work in pci_qdev_realize()
2230 if (pci_dev->acpi_index > ONBOARD_INDEX_MAX) { in pci_qdev_realize()
2231 error_setg(errp, "acpi-index should be less or equal to %u", in pci_qdev_realize()
2237 * make sure that acpi-index is unique across all present PCI devices in pci_qdev_realize()
2239 if (pci_dev->acpi_index) { in pci_qdev_realize()
2243 GINT_TO_POINTER(pci_dev->acpi_index), in pci_qdev_realize()
2245 error_setg(errp, "a PCI device with acpi-index = %" PRIu32 in pci_qdev_realize()
2246 " already exist", pci_dev->acpi_index); in pci_qdev_realize()
2250 GINT_TO_POINTER(pci_dev->acpi_index), in pci_qdev_realize()
2254 if (pci_dev->romsize != UINT32_MAX && !is_power_of_2(pci_dev->romsize)) { in pci_qdev_realize()
2255 error_setg(errp, "ROM size %u is not a power of two", pci_dev->romsize); in pci_qdev_realize()
2264 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS; in pci_qdev_realize()
2268 pci_dev->cap_present |= QEMU_PCIE_CAP_CXL; in pci_qdev_realize()
2273 pci_dev->devfn, errp); in pci_qdev_realize()
2277 if (pc->realize) { in pci_qdev_realize()
2278 pc->realize(pci_dev, &local_err); in pci_qdev_realize()
2296 * With ARI, PCI_SLOT() can return non-zero value as the traditional in pci_qdev_realize()
2297 * 5-bit Device Number and 3-bit Function Number fields in its associated in pci_qdev_realize()
2299 * single 8-bit Function Number. Hence, ignore ARI capable devices. in pci_qdev_realize()
2304 PCI_SLOT(pci_dev->devfn)) { in pci_qdev_realize()
2307 PCI_SLOT(pci_dev->devfn), pci_dev->name); in pci_qdev_realize()
2310 if (pci_dev->failover_pair_id) { in pci_qdev_realize()
2317 class_id = pci_get_word(pci_dev->config + PCI_CLASS_DEVICE); in pci_qdev_realize()
2324 if ((pci_dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) in pci_qdev_realize()
2325 || (PCI_FUNC(pci_dev->devfn) != 0)) { in pci_qdev_realize()
2331 qdev->allow_unplug_during_migration = true; in pci_qdev_realize()
2336 if (pci_dev->romfile == NULL && pc->romfile != NULL) { in pci_qdev_realize()
2337 pci_dev->romfile = g_strdup(pc->romfile); in pci_qdev_realize()
2350 pci_dev->msi_trigger = pci_msi_trigger; in pci_qdev_realize()
2376 return qdev_realize_and_unref(&dev->qdev, &bus->qbus, errp); in pci_realize_and_unref()
2399 if (pdev->used[i]) in pci_find_space()
2401 else if (i - offset + 1 == size) in pci_find_space()
2412 if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST)) in pci_find_capability_list()
2415 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]); in pci_find_capability_list()
2417 if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id) in pci_find_capability_list()
2429 if (!(pdev->used[offset])) { in pci_find_capability_at_offset()
2433 assert(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST); in pci_find_capability_at_offset()
2435 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]); in pci_find_capability_at_offset()
2444 /* Patch the PCI vendor and device ids in a PCI rom image if necessary.
2471 vendor_id = pci_get_word(pdev->config + PCI_VENDOR_ID); in pci_patch_ids()
2472 device_id = pci_get_word(pdev->config + PCI_DEVICE_ID); in pci_patch_ids()
2476 trace_pci_rom_and_pci_ids(pdev->romfile, vendor_id, device_id, in pci_patch_ids()
2482 /* Patch vendor id and checksum (at offset 6 for etherboot roms). */ in pci_patch_ids()
2484 checksum -= (uint8_t)vendor_id + (uint8_t)(vendor_id >> 8); in pci_patch_ids()
2491 /* Patch device id and checksum (at offset 6 for etherboot roms). */ in pci_patch_ids()
2493 checksum -= (uint8_t)device_id + (uint8_t)(device_id >> 8); in pci_patch_ids()
2516 if (!pdev->romfile || !strlen(pdev->romfile)) { in pci_add_option_rom()
2520 if (!pdev->rom_bar) { in pci_add_option_rom()
2525 int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE); in pci_add_option_rom()
2528 * Hot-plugged devices can't use the option ROM in pci_add_option_rom()
2531 if (DEVICE(pdev)->hotplugged) { in pci_add_option_rom()
2532 error_setg(errp, "Hot-plugged device without ROM bar" in pci_add_option_rom()
2538 rom_add_vga(pdev->romfile); in pci_add_option_rom()
2540 rom_add_option(pdev->romfile, -1); in pci_add_option_rom()
2546 if (pdev->rom_bar > 0) { in pci_add_option_rom()
2547 error_setg(errp, "ROM BAR cannot be enabled for SR-IOV VF"); in pci_add_option_rom()
2553 if (load_file || pdev->romsize == UINT32_MAX) { in pci_add_option_rom()
2554 path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile); in pci_add_option_rom()
2556 path = g_strdup(pdev->romfile); in pci_add_option_rom()
2561 error_setg(errp, "failed to find romfile \"%s\"", pdev->romfile); in pci_add_option_rom()
2564 error_setg(errp, "romfile \"%s\" is empty", pdev->romfile); in pci_add_option_rom()
2569 pdev->romfile); in pci_add_option_rom()
2572 if (pdev->romsize != UINT_MAX) { in pci_add_option_rom()
2573 if (size > pdev->romsize) { in pci_add_option_rom()
2576 pdev->romfile, (uint32_t)size, pdev->romsize); in pci_add_option_rom()
2580 pdev->romsize = pow2ceil(size); in pci_add_option_rom()
2586 vmsd ? vmsd->name : object_get_typename(OBJECT(pdev))); in pci_add_option_rom()
2588 pdev->has_rom = true; in pci_add_option_rom()
2589 memory_region_init_rom(&pdev->rom, OBJECT(pdev), name, pdev->romsize, in pci_add_option_rom()
2593 void *ptr = memory_region_get_ram_ptr(&pdev->rom); in pci_add_option_rom()
2596 error_setg(errp, "failed to load romfile \"%s\"", pdev->romfile); in pci_add_option_rom()
2606 pci_register_bar(pdev, PCI_ROM_SLOT, 0, &pdev->rom); in pci_add_option_rom()
2611 if (!pdev->has_rom) in pci_del_option_rom()
2614 vmstate_unregister_ram(&pdev->rom, &pdev->qdev); in pci_del_option_rom()
2615 pdev->has_rom = false; in pci_del_option_rom()
2637 * depends on this check to verify that the device is not broken. in pci_add_capability()
2647 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), in pci_add_capability()
2649 return -EINVAL; in pci_add_capability()
2654 config = pdev->config + offset; in pci_add_capability()
2656 config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST]; in pci_add_capability()
2657 pdev->config[PCI_CAPABILITY_LIST] = offset; in pci_add_capability()
2658 pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST; in pci_add_capability()
2659 memset(pdev->used + offset, 0xFF, QEMU_ALIGN_UP(size, 4)); in pci_add_capability()
2660 /* Make capability read-only by default */ in pci_add_capability()
2661 memset(pdev->wmask + offset, 0, size); in pci_add_capability()
2662 /* Check capability by default */ in pci_add_capability()
2663 memset(pdev->cmask + offset, 0xFF, size); in pci_add_capability()
2673 pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT]; in pci_del_capability()
2675 memset(pdev->wmask + offset, 0xff, size); in pci_del_capability()
2676 memset(pdev->w1cmask + offset, 0, size); in pci_del_capability()
2677 /* Clear cmask as device-specific registers can't be checked */ in pci_del_capability()
2678 memset(pdev->cmask + offset, 0, size); in pci_del_capability()
2679 memset(pdev->used + offset, 0, QEMU_ALIGN_UP(size, 4)); in pci_del_capability()
2681 if (!pdev->config[PCI_CAPABILITY_LIST]) in pci_del_capability()
2682 pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST; in pci_del_capability()
2695 int class = pci_get_word(d->config + PCI_CLASS_DEVICE); in pci_dev_fw_name()
2697 while (desc->desc && in pci_dev_fw_name()
2698 (class & ~desc->fw_ign_bits) != in pci_dev_fw_name()
2699 (desc->class & ~desc->fw_ign_bits)) { in pci_dev_fw_name()
2703 if (desc->desc) { in pci_dev_fw_name()
2704 name = desc->fw_name; in pci_dev_fw_name()
2711 pci_get_word(d->config + PCI_VENDOR_ID), in pci_dev_fw_name()
2712 pci_get_word(d->config + PCI_DEVICE_ID)); in pci_dev_fw_name()
2722 int has_func = !!PCI_FUNC(d->devfn); in pcibus_get_fw_dev_path()
2726 PCI_SLOT(d->devfn), in pcibus_get_fw_dev_path()
2729 PCI_FUNC(d->devfn)); in pcibus_get_fw_dev_path()
2745 int slot_len = sizeof slot - 1 /* For '\0' */; in pcibus_get_dev_path()
2755 for (t = d; t; t = pci_get_bus(t)->parent_dev) { in pcibus_get_dev_path()
2770 for (t = d; t; t = pci_get_bus(t)->parent_dev) { in pcibus_get_dev_path()
2771 p -= slot_len; in pcibus_get_dev_path()
2773 PCI_SLOT(t->devfn), PCI_FUNC(t->devfn)); in pcibus_get_dev_path()
2784 DeviceState *qdev = qdev_find_recursive(&bus->qbus, id); in pci_qdev_find_recursive()
2786 return -ENODEV; in pci_qdev_find_recursive()
2789 /* roughly check if given qdev is pci device */ in pci_qdev_find_recursive()
2794 return -EINVAL; in pci_qdev_find_recursive()
2800 int rc = -ENODEV; in pci_qdev_find_device()
2803 int tmp = pci_qdev_find_recursive(host_bridge->bus, id, pdev); in pci_qdev_find_device()
2808 if (tmp != -ENODEV) { in pci_qdev_find_device()
2818 return pci_get_bus(dev)->address_space_mem; in pci_address_space()
2823 return pci_get_bus(dev)->address_space_io; in pci_address_space_io()
2830 k->realize = pci_qdev_realize; in pci_device_class_init()
2831 k->unrealize = pci_qdev_unrealize; in pci_device_class_init()
2832 k->bus_type = TYPE_PCI_BUS; in pci_device_class_init()
2835 klass, "x-max-bounce-buffer-size", in pci_device_class_init()
2873 int devfn = dev->devfn; in pci_device_get_iommu_bus_devfn()
2875 while (iommu_bus && !iommu_bus->iommu_ops && iommu_bus->parent_dev) { in pci_device_get_iommu_bus_devfn()
2876 PCIBus *parent_bus = pci_get_bus(iommu_bus->parent_dev); in pci_device_get_iommu_bus_devfn()
2882 * conventional PCI buses pre-date such concepts. Instead, the PCIe- in pci_device_get_iommu_bus_devfn()
2883 * to-PCI bridge creates and accepts transactions on behalf of down- in pci_device_get_iommu_bus_devfn()
2886 * depends on the format of the bridge devices. Proper PCIe-to-PCI in pci_device_get_iommu_bus_devfn()
2888 * guidelines of chapter 2.3 of the PCIe-to-PCI/X bridge specification, in pci_device_get_iommu_bus_devfn()
2891 * found on the root complex such as the dmi-to-pci-bridge, we follow in pci_device_get_iommu_bus_devfn()
2892 * the convention of typical bare-metal hardware, which uses the in pci_device_get_iommu_bus_devfn()
2900 PCIDevice *parent = iommu_bus->parent_dev; in pci_device_get_iommu_bus_devfn()
2907 devfn = parent->devfn; in pci_device_get_iommu_bus_devfn()
2918 if (pci_bus_bypass_iommu(bus) || !iommu_bus->iommu_ops) { in pci_device_get_iommu_bus_devfn()
2941 return iommu_bus->iommu_ops->get_address_space(bus, in pci_device_iommu_address_space()
2942 iommu_bus->iommu_opaque, devfn); in pci_device_iommu_address_space()
2955 if (iommu_bus && iommu_bus->iommu_ops->init_iotlb_notifier) { in pci_iommu_init_iotlb_notifier()
2956 iommu_bus->iommu_ops->init_iotlb_notifier(bus, iommu_bus->iommu_opaque, in pci_iommu_init_iotlb_notifier()
2961 return -ENODEV; in pci_iommu_init_iotlb_notifier()
2973 if (iommu_bus && iommu_bus->iommu_ops->set_iommu_device) { in pci_device_set_iommu_device()
2974 hiod->aliased_bus = aliased_bus; in pci_device_set_iommu_device()
2975 hiod->aliased_devfn = aliased_devfn; in pci_device_set_iommu_device()
2976 return iommu_bus->iommu_ops->set_iommu_device(pci_get_bus(dev), in pci_device_set_iommu_device()
2977 iommu_bus->iommu_opaque, in pci_device_set_iommu_device()
2978 dev->devfn, hiod, errp); in pci_device_set_iommu_device()
2988 if (iommu_bus && iommu_bus->iommu_ops->unset_iommu_device) { in pci_device_unset_iommu_device()
2989 return iommu_bus->iommu_ops->unset_iommu_device(pci_get_bus(dev), in pci_device_unset_iommu_device()
2990 iommu_bus->iommu_opaque, in pci_device_unset_iommu_device()
2991 dev->devfn); in pci_device_unset_iommu_device()
3003 if (!dev->is_master || in pci_pri_request_page()
3005 return -EPERM; in pci_pri_request_page()
3009 return -EPERM; in pci_pri_request_page()
3013 if (iommu_bus && iommu_bus->iommu_ops->pri_request_page) { in pci_pri_request_page()
3014 return iommu_bus->iommu_ops->pri_request_page(bus, in pci_pri_request_page()
3015 iommu_bus->iommu_opaque, in pci_pri_request_page()
3021 return -ENODEV; in pci_pri_request_page()
3031 if (!dev->is_master || in pci_pri_register_notifier()
3033 return -EPERM; in pci_pri_register_notifier()
3037 if (iommu_bus && iommu_bus->iommu_ops->pri_register_notifier) { in pci_pri_register_notifier()
3038 iommu_bus->iommu_ops->pri_register_notifier(bus, in pci_pri_register_notifier()
3039 iommu_bus->iommu_opaque, in pci_pri_register_notifier()
3044 return -ENODEV; in pci_pri_register_notifier()
3054 if (iommu_bus && iommu_bus->iommu_ops->pri_unregister_notifier) { in pci_pri_unregister_notifier()
3055 iommu_bus->iommu_ops->pri_unregister_notifier(bus, in pci_pri_unregister_notifier()
3056 iommu_bus->iommu_opaque, in pci_pri_unregister_notifier()
3072 if (!dev->is_master || in pci_ats_request_translation()
3074 return -EPERM; in pci_ats_request_translation()
3078 return -ENOSPC; in pci_ats_request_translation()
3082 return -EPERM; in pci_ats_request_translation()
3086 if (iommu_bus && iommu_bus->iommu_ops->ats_request_translation) { in pci_ats_request_translation()
3087 return iommu_bus->iommu_ops->ats_request_translation(bus, in pci_ats_request_translation()
3088 iommu_bus->iommu_opaque, in pci_ats_request_translation()
3095 return -ENODEV; in pci_ats_request_translation()
3106 return -EPERM; in pci_iommu_register_iotlb_notifier()
3110 if (iommu_bus && iommu_bus->iommu_ops->register_iotlb_notifier) { in pci_iommu_register_iotlb_notifier()
3111 iommu_bus->iommu_ops->register_iotlb_notifier(bus, in pci_iommu_register_iotlb_notifier()
3112 iommu_bus->iommu_opaque, devfn, in pci_iommu_register_iotlb_notifier()
3117 return -ENODEV; in pci_iommu_register_iotlb_notifier()
3128 return -EPERM; in pci_iommu_unregister_iotlb_notifier()
3132 if (iommu_bus && iommu_bus->iommu_ops->unregister_iotlb_notifier) { in pci_iommu_unregister_iotlb_notifier()
3133 iommu_bus->iommu_ops->unregister_iotlb_notifier(bus, in pci_iommu_unregister_iotlb_notifier()
3134 iommu_bus->iommu_opaque, in pci_iommu_unregister_iotlb_notifier()
3139 return -ENODEV; in pci_iommu_unregister_iotlb_notifier()
3150 if (iommu_bus && iommu_bus->iommu_ops->get_iotlb_info) { in pci_iommu_get_iotlb_info()
3151 iommu_bus->iommu_ops->get_iotlb_info(iommu_bus->iommu_opaque, in pci_iommu_get_iotlb_info()
3156 return -ENODEV; in pci_iommu_get_iotlb_info()
3166 assert(ops->get_address_space); in pci_setup_iommu()
3168 bus->iommu_ops = ops; in pci_setup_iommu()
3169 bus->iommu_opaque = opaque; in pci_setup_iommu()
3175 uint16_t cmd = pci_get_word(dev->config + PCI_COMMAND); in pci_dev_get_w64()
3195 PCIIORegion *r = &dev->io_regions[i]; in pci_dev_get_w64()
3199 if (!r->size || in pci_dev_get_w64()
3200 (r->type & PCI_BASE_ADDRESS_SPACE_IO) || in pci_dev_get_w64()
3201 !(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64)) { in pci_dev_get_w64()
3205 lob = pci_bar_address(dev, i, r->type, r->size); in pci_dev_get_w64()
3206 upb = lob + r->size - 1; in pci_dev_get_w64()
3231 * As there are several types of these, it's easier to check the in pcie_has_upstream_port()
3237 parent_dev->exp.exp_cap && in pcie_has_upstream_port()
3248 return bus->devices[0]; in pci_get_function_0()
3250 /* Other bus types might support multiple devices at slots 0-31 */ in pci_get_function_0()
3251 return bus->devices[PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 0)]; in pci_get_function_0()
3276 * wait until the guest configures SR-IOV. in pci_set_power()
3287 if (d->enabled == state) { in pci_set_enabled()
3291 d->enabled = state; in pci_set_enabled()
3293 pci_set_master(d, (pci_get_word(d->config + PCI_COMMAND) in pci_set_enabled()
3294 & PCI_COMMAND_MASTER) && d->enabled); in pci_set_enabled()
3295 if (qdev_is_realized(&d->qdev)) { in pci_set_enabled()