Lines Matching full:ds
407 PnvPhb4DMASpace *ds; in pnv_phb4_rtc_invalidate() local
410 QLIST_FOREACH(ds, &phb->dma_spaces, list) { in pnv_phb4_rtc_invalidate()
411 ds->pe_num = PHB_INVALID_PE; in pnv_phb4_rtc_invalidate()
415 static void pnv_phb4_update_msi_regions(PnvPhb4DMASpace *ds) in pnv_phb4_update_msi_regions() argument
417 uint64_t cfg = ds->phb->regs[PHB_PHB4_CONFIG >> 3]; in pnv_phb4_update_msi_regions()
420 if (!memory_region_is_mapped(MEMORY_REGION(&ds->msi32_mr))) { in pnv_phb4_update_msi_regions()
421 memory_region_add_subregion(MEMORY_REGION(&ds->dma_mr), in pnv_phb4_update_msi_regions()
422 0xffff0000, &ds->msi32_mr); in pnv_phb4_update_msi_regions()
425 if (memory_region_is_mapped(MEMORY_REGION(&ds->msi32_mr))) { in pnv_phb4_update_msi_regions()
426 memory_region_del_subregion(MEMORY_REGION(&ds->dma_mr), in pnv_phb4_update_msi_regions()
427 &ds->msi32_mr); in pnv_phb4_update_msi_regions()
432 if (!memory_region_is_mapped(MEMORY_REGION(&ds->msi64_mr))) { in pnv_phb4_update_msi_regions()
433 memory_region_add_subregion(MEMORY_REGION(&ds->dma_mr), in pnv_phb4_update_msi_regions()
434 (1ull << 60), &ds->msi64_mr); in pnv_phb4_update_msi_regions()
437 if (memory_region_is_mapped(MEMORY_REGION(&ds->msi64_mr))) { in pnv_phb4_update_msi_regions()
438 memory_region_del_subregion(MEMORY_REGION(&ds->dma_mr), in pnv_phb4_update_msi_regions()
439 &ds->msi64_mr); in pnv_phb4_update_msi_regions()
446 PnvPhb4DMASpace *ds; in pnv_phb4_update_all_msi_regions() local
448 QLIST_FOREACH(ds, &phb->dma_spaces, list) { in pnv_phb4_update_all_msi_regions()
449 pnv_phb4_update_msi_regions(ds); in pnv_phb4_update_all_msi_regions()
1180 static bool pnv_phb4_resolve_pe(PnvPhb4DMASpace *ds) in pnv_phb4_resolve_pe() argument
1188 if (ds->pe_num != PHB_INVALID_PE) { in pnv_phb4_resolve_pe()
1193 rtt = ds->phb->regs[PHB_RTT_BAR >> 3]; in pnv_phb4_resolve_pe()
1195 phb_error(ds->phb, "DMA with RTT BAR disabled !"); in pnv_phb4_resolve_pe()
1201 bus_num = pci_bus_num(ds->bus); in pnv_phb4_resolve_pe()
1203 addr += 2 * PCI_BUILD_BDF(bus_num, ds->devfn); in pnv_phb4_resolve_pe()
1206 phb_error(ds->phb, "Failed to read RTT entry at 0x%"PRIx64, addr); in pnv_phb4_resolve_pe()
1213 num_PEs = ds->phb->big_phb ? PNV_PHB4_MAX_PEs : (PNV_PHB4_MAX_PEs >> 1); in pnv_phb4_resolve_pe()
1215 phb_error(ds->phb, "RTE for RID 0x%x invalid (%04x", ds->devfn, rte); in pnv_phb4_resolve_pe()
1218 ds->pe_num = rte; in pnv_phb4_resolve_pe()
1222 static void pnv_phb4_translate_tve(PnvPhb4DMASpace *ds, hwaddr addr, in pnv_phb4_translate_tve() argument
1233 phb_error(ds->phb, "Invalid #levels in TVE %d", lev); in pnv_phb4_translate_tve()
1239 phb_error(ds->phb, "Access to invalid TVE"); in pnv_phb4_translate_tve()
1278 phb_error(ds->phb, "Failed to read TCE at 0x%"PRIx64, taddr); in pnv_phb4_translate_tve()
1285 phb_error(ds->phb, "Invalid indirect TCE at 0x%"PRIx64, taddr); in pnv_phb4_translate_tve()
1286 phb_error(ds->phb, " xlate %"PRIx64":%c TVE=%"PRIx64, addr, in pnv_phb4_translate_tve()
1288 phb_error(ds->phb, " tta=%"PRIx64" lev=%d tts=%d tps=%d", in pnv_phb4_translate_tve()
1298 phb_error(ds->phb, "TCE access fault at 0x%"PRIx64, taddr); in pnv_phb4_translate_tve()
1299 phb_error(ds->phb, " xlate %"PRIx64":%c TVE=%"PRIx64, addr, in pnv_phb4_translate_tve()
1301 phb_error(ds->phb, " tta=%"PRIx64" lev=%d tts=%d tps=%d", in pnv_phb4_translate_tve()
1318 PnvPhb4DMASpace *ds = container_of(iommu, PnvPhb4DMASpace, dma_mr); in pnv_phb4_translate_iommu() local
1330 if (!pnv_phb4_resolve_pe(ds)) { in pnv_phb4_translate_iommu()
1331 phb_error(ds->phb, "Failed to resolve PE# for bus @%p (%d) devfn 0x%x", in pnv_phb4_translate_iommu()
1332 ds->bus, pci_bus_num(ds->bus), ds->devfn); in pnv_phb4_translate_iommu()
1340 cfg = ds->phb->regs[PHB_PHB4_CONFIG >> 3]; in pnv_phb4_translate_iommu()
1343 phb_error(ds->phb, "xlate on 32-bit MSI region"); in pnv_phb4_translate_iommu()
1348 tve = ds->phb->ioda_TVT[ds->pe_num * 2 + tve_sel]; in pnv_phb4_translate_iommu()
1349 pnv_phb4_translate_tve(ds, addr, flag & IOMMU_WO, tve, &ret); in pnv_phb4_translate_iommu()
1352 phb_error(ds->phb, "xlate on 64-bit MSI region"); in pnv_phb4_translate_iommu()
1355 phb_error(ds->phb, "xlate on unsupported address 0x%"PRIx64, addr); in pnv_phb4_translate_iommu()
1402 PnvPhb4DMASpace *ds = opaque; in pnv_phb4_msi_write() local
1403 PnvPHB4 *phb = ds->phb; in pnv_phb4_msi_write()
1408 if (!pnv_phb4_resolve_pe(ds)) { in pnv_phb4_msi_write()
1410 ds->bus, pci_bus_num(ds->bus), ds->devfn); in pnv_phb4_msi_write()
1428 PnvPhb4DMASpace *ds = opaque; in pnv_phb4_msi_read() local
1430 phb_error(ds->phb, "Invalid MSI read @ 0x%" HWADDR_PRIx, addr); in pnv_phb4_msi_read()
1442 PnvPhb4DMASpace *ds; in pnv_phb4_dma_find() local
1444 QLIST_FOREACH(ds, &phb->dma_spaces, list) { in pnv_phb4_dma_find()
1445 if (ds->bus == bus && ds->devfn == devfn) { in pnv_phb4_dma_find()
1449 return ds; in pnv_phb4_dma_find()
1455 PnvPhb4DMASpace *ds; in pnv_phb4_dma_iommu() local
1458 ds = pnv_phb4_dma_find(phb, bus, devfn); in pnv_phb4_dma_iommu()
1460 if (ds == NULL) { in pnv_phb4_dma_iommu()
1461 ds = g_new0(PnvPhb4DMASpace, 1); in pnv_phb4_dma_iommu()
1462 ds->bus = bus; in pnv_phb4_dma_iommu()
1463 ds->devfn = devfn; in pnv_phb4_dma_iommu()
1464 ds->pe_num = PHB_INVALID_PE; in pnv_phb4_dma_iommu()
1465 ds->phb = phb; in pnv_phb4_dma_iommu()
1468 memory_region_init_iommu(&ds->dma_mr, sizeof(ds->dma_mr), in pnv_phb4_dma_iommu()
1471 address_space_init(&ds->dma_as, MEMORY_REGION(&ds->dma_mr), in pnv_phb4_dma_iommu()
1473 memory_region_init_io(&ds->msi32_mr, OBJECT(phb), &pnv_phb4_msi_ops, in pnv_phb4_dma_iommu()
1474 ds, "msi32", 0x10000); in pnv_phb4_dma_iommu()
1475 memory_region_init_io(&ds->msi64_mr, OBJECT(phb), &pnv_phb4_msi_ops, in pnv_phb4_dma_iommu()
1476 ds, "msi64", 0x100000); in pnv_phb4_dma_iommu()
1477 pnv_phb4_update_msi_regions(ds); in pnv_phb4_dma_iommu()
1479 QLIST_INSERT_HEAD(&phb->dma_spaces, ds, list); in pnv_phb4_dma_iommu()
1481 return &ds->dma_as; in pnv_phb4_dma_iommu()