423     PnvPhb3DMASpace *ds;  in pnv_phb3_rtc_invalidate()  local
426     QLIST_FOREACH(ds, &phb->dma_spaces, list) {  in pnv_phb3_rtc_invalidate()
427         ds->pe_num = PHB_INVALID_PE;  in pnv_phb3_rtc_invalidate()
432 static void pnv_phb3_update_msi_regions(PnvPhb3DMASpace *ds)  in pnv_phb3_update_msi_regions()  argument
434     uint64_t cfg = ds->phb->regs[PHB_PHB3_CONFIG >> 3];  in pnv_phb3_update_msi_regions()
437         if (!memory_region_is_mapped(&ds->msi32_mr)) {  in pnv_phb3_update_msi_regions()
438             memory_region_add_subregion(MEMORY_REGION(&ds->dma_mr),  in pnv_phb3_update_msi_regions()
439                                         0xffff0000, &ds->msi32_mr);  in pnv_phb3_update_msi_regions()
442         if (memory_region_is_mapped(&ds->msi32_mr)) {  in pnv_phb3_update_msi_regions()
443             memory_region_del_subregion(MEMORY_REGION(&ds->dma_mr),  in pnv_phb3_update_msi_regions()
444                                         &ds->msi32_mr);  in pnv_phb3_update_msi_regions()
449         if (!memory_region_is_mapped(&ds->msi64_mr)) {  in pnv_phb3_update_msi_regions()
450             memory_region_add_subregion(MEMORY_REGION(&ds->dma_mr),  in pnv_phb3_update_msi_regions()
451                                         (1ull << 60), &ds->msi64_mr);  in pnv_phb3_update_msi_regions()
454         if (memory_region_is_mapped(&ds->msi64_mr)) {  in pnv_phb3_update_msi_regions()
455             memory_region_del_subregion(MEMORY_REGION(&ds->dma_mr),  in pnv_phb3_update_msi_regions()
456                                         &ds->msi64_mr);  in pnv_phb3_update_msi_regions()
463     PnvPhb3DMASpace *ds;  in pnv_phb3_update_all_msi_regions()  local
465     QLIST_FOREACH(ds, &phb->dma_spaces, list) {  in pnv_phb3_update_all_msi_regions()
466         pnv_phb3_update_msi_regions(ds);  in pnv_phb3_update_all_msi_regions()
697 static bool pnv_phb3_resolve_pe(PnvPhb3DMASpace *ds)  in pnv_phb3_resolve_pe()  argument
704     if (ds->pe_num != PHB_INVALID_PE) {  in pnv_phb3_resolve_pe()
709     rtt = ds->phb->regs[PHB_RTT_BAR >> 3];  in pnv_phb3_resolve_pe()
711         phb3_error(ds->phb, "DMA with RTT BAR disabled !");  in pnv_phb3_resolve_pe()
717     bus_num = pci_bus_num(ds->bus);  in pnv_phb3_resolve_pe()
719     addr += 2 * ((bus_num << 8) | ds->devfn);  in pnv_phb3_resolve_pe()
722         phb3_error(ds->phb, "Failed to read RTT entry at 0x%"PRIx64, addr);  in pnv_phb3_resolve_pe()
730         phb3_error(ds->phb, "RTE for RID 0x%x invalid (%04x", ds->devfn, rte);  in pnv_phb3_resolve_pe()
734     ds->pe_num = rte;  in pnv_phb3_resolve_pe()
738 static void pnv_phb3_translate_tve(PnvPhb3DMASpace *ds, hwaddr addr,  in pnv_phb3_translate_tve()  argument
746     PnvPHB3 *phb = ds->phb;  in pnv_phb3_translate_tve()
843     PnvPhb3DMASpace *ds = container_of(iommu, PnvPhb3DMASpace, dma_mr);  in pnv_phb3_translate_iommu()  local
853     PnvPHB3 *phb = ds->phb;  in pnv_phb3_translate_iommu()
856     if (!pnv_phb3_resolve_pe(ds)) {  in pnv_phb3_translate_iommu()
858                    ds->bus, pci_bus_num(ds->bus), ds->devfn);  in pnv_phb3_translate_iommu()
866         cfg = ds->phb->regs[PHB_PHB3_CONFIG >> 3];  in pnv_phb3_translate_iommu()
874         tve = ds->phb->ioda_TVT[ds->pe_num * 2 + tve_sel];  in pnv_phb3_translate_iommu()
875         pnv_phb3_translate_tve(ds, addr, flag & IOMMU_WO, tve, &ret);  in pnv_phb3_translate_iommu()
911     PnvPhb3DMASpace *ds = opaque;  in pnv_phb3_msi_write()  local
914     if (!pnv_phb3_resolve_pe(ds)) {  in pnv_phb3_msi_write()
915         phb3_error(ds->phb, "Failed to resolve PE# for bus @%p (%d) devfn 0x%x",  in pnv_phb3_msi_write()
916                    ds->bus, pci_bus_num(ds->bus), ds->devfn);  in pnv_phb3_msi_write()
920     pnv_phb3_msi_send(&ds->phb->msis, addr, data, ds->pe_num);  in pnv_phb3_msi_write()
926     PnvPhb3DMASpace *ds = opaque;  in pnv_phb3_msi_read()  local
928     phb3_error(ds->phb, "invalid read @ 0x%" HWADDR_PRIx, addr);  in pnv_phb3_msi_read()
941     PnvPhb3DMASpace *ds;  in pnv_phb3_dma_iommu()  local
943     QLIST_FOREACH(ds, &phb->dma_spaces, list) {  in pnv_phb3_dma_iommu()
944         if (ds->bus == bus && ds->devfn == devfn) {  in pnv_phb3_dma_iommu()
949     if (ds == NULL) {  in pnv_phb3_dma_iommu()
950         ds = g_new0(PnvPhb3DMASpace, 1);  in pnv_phb3_dma_iommu()
951         ds->bus = bus;  in pnv_phb3_dma_iommu()
952         ds->devfn = devfn;  in pnv_phb3_dma_iommu()
953         ds->pe_num = PHB_INVALID_PE;  in pnv_phb3_dma_iommu()
954         ds->phb = phb;  in pnv_phb3_dma_iommu()
955         memory_region_init_iommu(&ds->dma_mr, sizeof(ds->dma_mr),  in pnv_phb3_dma_iommu()
958         address_space_init(&ds->dma_as, MEMORY_REGION(&ds->dma_mr),  in pnv_phb3_dma_iommu()
960         memory_region_init_io(&ds->msi32_mr, OBJECT(phb), &pnv_phb3_msi_ops,  in pnv_phb3_dma_iommu()
961                               ds, "msi32", 0x10000);  in pnv_phb3_dma_iommu()
962         memory_region_init_io(&ds->msi64_mr, OBJECT(phb), &pnv_phb3_msi_ops,  in pnv_phb3_dma_iommu()
963                               ds, "msi64", 0x100000);  in pnv_phb3_dma_iommu()
964         pnv_phb3_update_msi_regions(ds);  in pnv_phb3_dma_iommu()
966         QLIST_INSERT_HEAD(&phb->dma_spaces, ds, list);  in pnv_phb3_dma_iommu()
968     return &ds->dma_as;  in pnv_phb3_dma_iommu()