Lines Matching +full:- +full:- +full:version

6  * This code is licensed under the GPL version 2 or later. See the
7 * COPYING file in the top-level directory.
14 #include "hw/pci-host/pnv_phb.h"
15 #include "hw/pci-host/pnv_phb3.h"
16 #include "hw/pci-host/pnv_phb4.h"
18 #include "hw/qdev-properties.h"
31 * which in turn calls the property release callback prop->release if
47 const char *dev_id = DEVICE(child)->id; in pnv_parent_fixup()
49 if (child->parent == parent) { in pnv_parent_fixup()
67 if (phb->version == 3) { in pnv_phb_user_get_parent()
83 PnvChip *chip = pnv_get_chip(pnv, phb->chip_id); in pnv_phb_user_device_init()
87 error_setg(errp, "invalid chip id: %d", phb->chip_id); in pnv_phb_user_device_init()
102 OBJECT(phb), phb->phb_id, errp)) { in pnv_phb_user_device_init()
115 if (!phb->version) { in pnv_phb_realize()
116 error_setg(errp, "version not specified"); in pnv_phb_realize()
120 switch (phb->version) { in pnv_phb_realize()
134 phb->backend = object_new(phb_typename); in pnv_phb_realize()
135 object_property_add_child(OBJECT(dev), "phb-backend", phb->backend); in pnv_phb_realize()
138 object_property_set_uint(phb->backend, "index", phb->phb_id, errp); in pnv_phb_realize()
139 object_property_set_uint(phb->backend, "chip-id", phb->chip_id, errp); in pnv_phb_realize()
140 object_property_set_link(phb->backend, "phb-base", OBJECT(phb), errp); in pnv_phb_realize()
146 if (!phb->chip && !phb->pec) { in pnv_phb_realize()
152 if (phb->version == 3) { in pnv_phb_realize()
153 object_property_set_link(phb->backend, "chip", in pnv_phb_realize()
154 OBJECT(phb->chip), errp); in pnv_phb_realize()
156 object_property_set_link(phb->backend, "pec", OBJECT(phb->pec), errp); in pnv_phb_realize()
159 if (!qdev_realize(DEVICE(phb->backend), NULL, errp)) { in pnv_phb_realize()
163 if (phb->version == 3) { in pnv_phb_realize()
164 pnv_phb3_bus_init(dev, PNV_PHB3(phb->backend)); in pnv_phb_realize()
166 pnv_phb4_bus_init(dev, PNV_PHB4(phb->backend)); in pnv_phb_realize()
172 pci_realize_and_unref(root, pci->bus, errp); in pnv_phb_realize()
181 snprintf(phb->bus_path, sizeof(phb->bus_path), "00%02x:%02x", in pnv_phb_root_bus_path()
182 phb->chip_id, phb->phb_id); in pnv_phb_root_bus_path()
183 return phb->bus_path; in pnv_phb_root_bus_path()
188 DEFINE_PROP_UINT32("chip-id", PnvPHB, chip_id, 0),
189 DEFINE_PROP_UINT32("version", PnvPHB, version, 0),
202 hc->root_bus_path = pnv_phb_root_bus_path; in pnv_phb_class_init()
203 dc->realize = pnv_phb_realize; in pnv_phb_class_init()
205 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); in pnv_phb_class_init()
206 dc->user_creatable = true; in pnv_phb_class_init()
214 uint8_t *conf = d->config; in pnv_phb_root_port_reset_hold()
216 if (rpc->parent_phases.hold) { in pnv_phb_root_port_reset_hold()
217 rpc->parent_phases.hold(obj, type); in pnv_phb_root_port_reset_hold()
220 if (phb_rp->version == 3) { in pnv_phb_root_port_reset_hold()
253 chip_id = object_property_get_int(OBJECT(bus), "chip-id", &local_err); in pnv_phb_root_port_realize()
258 index = object_property_get_int(OBJECT(bus), "phb-id", &local_err); in pnv_phb_root_port_realize()
279 rpc->parent_realize(dev, &local_err); in pnv_phb_root_port_realize()
285 switch (phb_rp->version) { in pnv_phb_root_port_realize()
299 pci_config_set_device_id(pci->config, device_id); in pnv_phb_root_port_realize()
300 pci_config_set_interrupt_pin(pci->config, 0); in pnv_phb_root_port_realize()
304 DEFINE_PROP_UINT32("version", PnvPHBRootPort, version, 0),
314 dc->desc = "IBM PHB PCIE Root Port"; in pnv_phb_root_port_class_init()
318 &rpc->parent_realize); in pnv_phb_root_port_class_init()
320 NULL, &rpc->parent_phases); in pnv_phb_root_port_class_init()
321 dc->user_creatable = true; in pnv_phb_root_port_class_init()
323 k->vendor_id = PCI_VENDOR_ID_IBM; in pnv_phb_root_port_class_init()
325 k->device_id = 0; in pnv_phb_root_port_class_init()
326 k->revision = 0; in pnv_phb_root_port_class_init()
328 rpc->exp_offset = 0x48; in pnv_phb_root_port_class_init()
329 rpc->aer_offset = 0x100; in pnv_phb_root_port_class_init()