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42 #define GT_REGS (0x1000 >> 2)
45 #define GT_CPU (0x000 >> 2)
46 #define GT_MULTI (0x120 >> 2)
52 #define GT_SCS10LD (0x008 >> 2)
53 #define GT_SCS10HD (0x010 >> 2)
54 #define GT_SCS32LD (0x018 >> 2)
55 #define GT_SCS32HD (0x020 >> 2)
56 #define GT_CS20LD (0x028 >> 2)
57 #define GT_CS20HD (0x030 >> 2)
58 #define GT_CS3BOOTLD (0x038 >> 2)
59 #define GT_CS3BOOTHD (0x040 >> 2)
60 #define GT_PCI0IOLD (0x048 >> 2)
61 #define GT_PCI0IOHD (0x050 >> 2)
62 #define GT_PCI0M0LD (0x058 >> 2)
63 #define GT_PCI0M0HD (0x060 >> 2)
64 #define GT_PCI0M1LD (0x080 >> 2)
65 #define GT_PCI0M1HD (0x088 >> 2)
66 #define GT_PCI1IOLD (0x090 >> 2)
67 #define GT_PCI1IOHD (0x098 >> 2)
68 #define GT_PCI1M0LD (0x0a0 >> 2)
69 #define GT_PCI1M0HD (0x0a8 >> 2)
70 #define GT_PCI1M1LD (0x0b0 >> 2)
71 #define GT_PCI1M1HD (0x0b8 >> 2)
72 #define GT_ISD (0x068 >> 2)
74 #define GT_SCS10AR (0x0d0 >> 2)
75 #define GT_SCS32AR (0x0d8 >> 2)
76 #define GT_CS20R (0x0e0 >> 2)
77 #define GT_CS3BOOTR (0x0e8 >> 2)
79 #define GT_PCI0IOREMAP (0x0f0 >> 2)
80 #define GT_PCI0M0REMAP (0x0f8 >> 2)
81 #define GT_PCI0M1REMAP (0x100 >> 2)
82 #define GT_PCI1IOREMAP (0x108 >> 2)
83 #define GT_PCI1M0REMAP (0x110 >> 2)
84 #define GT_PCI1M1REMAP (0x118 >> 2)
87 #define GT_CPUERR_ADDRLO (0x070 >> 2)
88 #define GT_CPUERR_ADDRHI (0x078 >> 2)
89 #define GT_CPUERR_DATALO (0x128 >> 2) /* GT-64120A only */
90 #define GT_CPUERR_DATAHI (0x130 >> 2) /* GT-64120A only */
91 #define GT_CPUERR_PARITY (0x138 >> 2) /* GT-64120A only */
94 #define GT_PCI0SYNC (0x0c0 >> 2)
95 #define GT_PCI1SYNC (0x0c8 >> 2)
98 #define GT_SCS0LD (0x400 >> 2)
99 #define GT_SCS0HD (0x404 >> 2)
100 #define GT_SCS1LD (0x408 >> 2)
101 #define GT_SCS1HD (0x40c >> 2)
102 #define GT_SCS2LD (0x410 >> 2)
103 #define GT_SCS2HD (0x414 >> 2)
104 #define GT_SCS3LD (0x418 >> 2)
105 #define GT_SCS3HD (0x41c >> 2)
106 #define GT_CS0LD (0x420 >> 2)
107 #define GT_CS0HD (0x424 >> 2)
108 #define GT_CS1LD (0x428 >> 2)
109 #define GT_CS1HD (0x42c >> 2)
110 #define GT_CS2LD (0x430 >> 2)
111 #define GT_CS2HD (0x434 >> 2)
112 #define GT_CS3LD (0x438 >> 2)
113 #define GT_CS3HD (0x43c >> 2)
114 #define GT_BOOTLD (0x440 >> 2)
115 #define GT_BOOTHD (0x444 >> 2)
116 #define GT_ADERR (0x470 >> 2)
119 #define GT_SDRAM_CFG (0x448 >> 2)
120 #define GT_SDRAM_OPMODE (0x474 >> 2)
121 #define GT_SDRAM_BM (0x478 >> 2)
122 #define GT_SDRAM_ADDRDECODE (0x47c >> 2)
125 #define GT_SDRAM_B0 (0x44c >> 2)
126 #define GT_SDRAM_B1 (0x450 >> 2)
127 #define GT_SDRAM_B2 (0x454 >> 2)
128 #define GT_SDRAM_B3 (0x458 >> 2)
131 #define GT_DEV_B0 (0x45c >> 2)
132 #define GT_DEV_B1 (0x460 >> 2)
133 #define GT_DEV_B2 (0x464 >> 2)
134 #define GT_DEV_B3 (0x468 >> 2)
135 #define GT_DEV_BOOT (0x46c >> 2)
138 #define GT_ECC_ERRDATALO (0x480 >> 2) /* GT-64120A only */
139 #define GT_ECC_ERRDATAHI (0x484 >> 2) /* GT-64120A only */
140 #define GT_ECC_MEM (0x488 >> 2) /* GT-64120A only */
141 #define GT_ECC_CALC (0x48c >> 2) /* GT-64120A only */
142 #define GT_ECC_ERRADDR (0x490 >> 2) /* GT-64120A only */
145 #define GT_DMA0_CNT (0x800 >> 2)
146 #define GT_DMA1_CNT (0x804 >> 2)
147 #define GT_DMA2_CNT (0x808 >> 2)
148 #define GT_DMA3_CNT (0x80c >> 2)
149 #define GT_DMA0_SA (0x810 >> 2)
150 #define GT_DMA1_SA (0x814 >> 2)
151 #define GT_DMA2_SA (0x818 >> 2)
152 #define GT_DMA3_SA (0x81c >> 2)
153 #define GT_DMA0_DA (0x820 >> 2)
154 #define GT_DMA1_DA (0x824 >> 2)
155 #define GT_DMA2_DA (0x828 >> 2)
156 #define GT_DMA3_DA (0x82c >> 2)
157 #define GT_DMA0_NEXT (0x830 >> 2)
158 #define GT_DMA1_NEXT (0x834 >> 2)
159 #define GT_DMA2_NEXT (0x838 >> 2)
160 #define GT_DMA3_NEXT (0x83c >> 2)
161 #define GT_DMA0_CUR (0x870 >> 2)
162 #define GT_DMA1_CUR (0x874 >> 2)
163 #define GT_DMA2_CUR (0x878 >> 2)
164 #define GT_DMA3_CUR (0x87c >> 2)
167 #define GT_DMA0_CTRL (0x840 >> 2)
168 #define GT_DMA1_CTRL (0x844 >> 2)
169 #define GT_DMA2_CTRL (0x848 >> 2)
170 #define GT_DMA3_CTRL (0x84c >> 2)
173 #define GT_DMA_ARB (0x860 >> 2)
176 #define GT_TC0 (0x850 >> 2)
177 #define GT_TC1 (0x854 >> 2)
178 #define GT_TC2 (0x858 >> 2)
179 #define GT_TC3 (0x85c >> 2)
180 #define GT_TC_CONTROL (0x864 >> 2)
183 #define GT_PCI0_CMD (0xc00 >> 2)
184 #define GT_PCI0_TOR (0xc04 >> 2)
185 #define GT_PCI0_BS_SCS10 (0xc08 >> 2)
186 #define GT_PCI0_BS_SCS32 (0xc0c >> 2)
187 #define GT_PCI0_BS_CS20 (0xc10 >> 2)
188 #define GT_PCI0_BS_CS3BT (0xc14 >> 2)
189 #define GT_PCI1_IACK (0xc30 >> 2)
190 #define GT_PCI0_IACK (0xc34 >> 2)
191 #define GT_PCI0_BARE (0xc3c >> 2)
192 #define GT_PCI0_PREFMBR (0xc40 >> 2)
193 #define GT_PCI0_SCS10_BAR (0xc48 >> 2)
194 #define GT_PCI0_SCS32_BAR (0xc4c >> 2)
195 #define GT_PCI0_CS20_BAR (0xc50 >> 2)
196 #define GT_PCI0_CS3BT_BAR (0xc54 >> 2)
197 #define GT_PCI0_SSCS10_BAR (0xc58 >> 2)
198 #define GT_PCI0_SSCS32_BAR (0xc5c >> 2)
199 #define GT_PCI0_SCS3BT_BAR (0xc64 >> 2)
200 #define GT_PCI1_CMD (0xc80 >> 2)
201 #define GT_PCI1_TOR (0xc84 >> 2)
202 #define GT_PCI1_BS_SCS10 (0xc88 >> 2)
203 #define GT_PCI1_BS_SCS32 (0xc8c >> 2)
204 #define GT_PCI1_BS_CS20 (0xc90 >> 2)
205 #define GT_PCI1_BS_CS3BT (0xc94 >> 2)
206 #define GT_PCI1_BARE (0xcbc >> 2)
207 #define GT_PCI1_PREFMBR (0xcc0 >> 2)
208 #define GT_PCI1_SCS10_BAR (0xcc8 >> 2)
209 #define GT_PCI1_SCS32_BAR (0xccc >> 2)
210 #define GT_PCI1_CS20_BAR (0xcd0 >> 2)
211 #define GT_PCI1_CS3BT_BAR (0xcd4 >> 2)
212 #define GT_PCI1_SSCS10_BAR (0xcd8 >> 2)
213 #define GT_PCI1_SSCS32_BAR (0xcdc >> 2)
214 #define GT_PCI1_SCS3BT_BAR (0xce4 >> 2)
215 #define GT_PCI1_CFGADDR (0xcf0 >> 2)
216 #define GT_PCI1_CFGDATA (0xcf4 >> 2)
217 #define GT_PCI0_CFGADDR (0xcf8 >> 2)
218 #define GT_PCI0_CFGDATA (0xcfc >> 2)
232 #define GT_INTRCAUSE (0xc18 >> 2)
233 #define GT_INTRMASK (0xc1c >> 2)
234 #define GT_PCI0_ICMASK (0xc24 >> 2)
235 #define GT_PCI0_SERR0MASK (0xc28 >> 2)
236 #define GT_CPU_INTSEL (0xc70 >> 2)
237 #define GT_PCI0_INTSEL (0xc74 >> 2)
238 #define GT_HINTRCAUSE (0xc98 >> 2)
239 #define GT_HINTRMASK (0xc9c >> 2)
240 #define GT_PCI0_HICMASK (0xca4 >> 2)
241 #define GT_PCI1_SERR1MASK (0xca8 >> 2)
414 uint32_t saddr = addr >> 2; in gt64120_writel()
494 saddr << 2, size, size << 1, val); in gt64120_writel()
504 saddr << 2, size, size << 1, val); in gt64120_writel()
546 saddr << 2, size, size << 1, val); in gt64120_writel()
559 saddr << 2, size, size << 1, val); in gt64120_writel()
596 saddr << 2, size, size << 1, val); in gt64120_writel()
609 saddr << 2, size, size << 1, val); in gt64120_writel()
653 saddr << 2, size, size << 1, val); in gt64120_writel()
706 saddr << 2, size, size << 1, val); in gt64120_writel()
716 uint32_t saddr = addr >> 2; in gt64120_readl()
972 saddr << 2, size, size << 1, val); in gt64120_readl()
1210 memory_region_add_subregion_overlap(&s->ISD_mem, GT_PCI0_CFGADDR << 2, in gt64120_realize()
1216 memory_region_add_subregion_overlap(&s->ISD_mem, GT_PCI0_CFGDATA << 2, in gt64120_realize()
1233 pci_set_long(d->wmask + PCI_BASE_ADDRESS_1, 0xfffff008); /* SCS[3:2] */ in gt64120_pci_realize()
1234 pci_set_long(d->wmask + PCI_BASE_ADDRESS_2, 0xfffff008); /* CS[2:0] */ in gt64120_pci_realize()