Lines Matching +full:uuid +full:- +full:dev
2 #include "hw/acpi/aml-build.h"
3 #include "hw/pci-host/gpex.h"
10 static void acpi_dsdt_add_pci_route_table(Aml *dev, uint32_t irq, in acpi_dsdt_add_pci_route_table() argument
29 aml_append(dev, aml_name_decl("_PRT", rt_pkg)); in acpi_dsdt_add_pci_route_table()
53 static void acpi_dsdt_add_pci_osc(Aml *dev) in acpi_dsdt_add_pci_osc() argument
55 Aml *method, *UUID, *ifctx, *ifctx1, *elsectx, *buf; in acpi_dsdt_add_pci_osc() local
58 aml_append(dev, aml_name_decl("SUPP", aml_int(0))); in acpi_dsdt_add_pci_osc()
59 aml_append(dev, aml_name_decl("CTRL", aml_int(0))); in acpi_dsdt_add_pci_osc()
66 * The _OSC interface for a PCI/PCI-X/PCI Express hierarchy is in acpi_dsdt_add_pci_osc()
67 * identified by the Universal Unique IDentifier (UUID) in acpi_dsdt_add_pci_osc()
68 * 33DB4D5B-1FF7-401C-9657-7441C03DD766 in acpi_dsdt_add_pci_osc()
70 UUID = aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766"); in acpi_dsdt_add_pci_osc()
71 ifctx = aml_if(aml_equal(aml_arg(0), UUID)); in acpi_dsdt_add_pci_osc()
105 aml_append(dev, method); in acpi_dsdt_add_pci_osc()
111 * The UUID in _DSM in this context is in acpi_dsdt_add_pci_osc()
112 * {E5C937D0-3553-4D7A-9117-EA4D19C3434D} in acpi_dsdt_add_pci_osc()
114 UUID = aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D"); in acpi_dsdt_add_pci_osc()
115 ifctx = aml_if(aml_equal(aml_arg(0), UUID)); in acpi_dsdt_add_pci_osc()
126 aml_append(dev, method); in acpi_dsdt_add_pci_osc()
131 int nr_pcie_buses = cfg->ecam.size / PCIE_MMCFG_SIZE_MIN; in acpi_dsdt_add_gpex()
132 Aml *method, *crs, *dev, *rbuf; in acpi_dsdt_add_gpex() local
133 PCIBus *bus = cfg->bus; in acpi_dsdt_add_gpex()
141 QLIST_FOREACH(bus, &bus->child, sibling) { in acpi_dsdt_add_gpex()
152 * 0 - (nr_pcie_buses - 1) is the bus range for the main in acpi_dsdt_add_gpex()
153 * host-bridge and it equals the MIN of the in acpi_dsdt_add_gpex()
154 * busNr defined for pxb-pcie. in acpi_dsdt_add_gpex()
162 dev = aml_device("PC%.02X", bus_num); in acpi_dsdt_add_gpex()
165 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0016"))); in acpi_dsdt_add_gpex()
168 aml_append(dev, aml_name_decl("_CID", pkg)); in acpi_dsdt_add_gpex()
170 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08"))); in acpi_dsdt_add_gpex()
171 aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03"))); in acpi_dsdt_add_gpex()
173 aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num))); in acpi_dsdt_add_gpex()
174 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); in acpi_dsdt_add_gpex()
175 aml_append(dev, aml_name_decl("_STR", aml_unicode("pxb Device"))); in acpi_dsdt_add_gpex()
176 aml_append(dev, aml_name_decl("_CCA", aml_int(1))); in acpi_dsdt_add_gpex()
178 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node))); in acpi_dsdt_add_gpex()
181 acpi_dsdt_add_pci_route_table(dev, cfg->irq, scope, bus_num); in acpi_dsdt_add_gpex()
185 * 1. The resources the pci-bridge/pcie-root-port need. in acpi_dsdt_add_gpex()
188 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set, in acpi_dsdt_add_gpex()
189 cfg->pio.base, 0, 0, 0); in acpi_dsdt_add_gpex()
190 aml_append(dev, aml_name_decl("_CRS", crs)); in acpi_dsdt_add_gpex()
193 build_cxl_osc_method(dev); in acpi_dsdt_add_gpex()
195 acpi_dsdt_add_pci_osc(dev); in acpi_dsdt_add_gpex()
198 aml_append(scope, dev); in acpi_dsdt_add_gpex()
203 dev = aml_device("%s", "PCI0"); in acpi_dsdt_add_gpex()
204 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08"))); in acpi_dsdt_add_gpex()
205 aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03"))); in acpi_dsdt_add_gpex()
206 aml_append(dev, aml_name_decl("_SEG", aml_int(0))); in acpi_dsdt_add_gpex()
207 aml_append(dev, aml_name_decl("_BBN", aml_int(0))); in acpi_dsdt_add_gpex()
208 aml_append(dev, aml_name_decl("_UID", aml_int(0))); in acpi_dsdt_add_gpex()
209 aml_append(dev, aml_name_decl("_STR", aml_unicode("PCIe 0 Device"))); in acpi_dsdt_add_gpex()
210 aml_append(dev, aml_name_decl("_CCA", aml_int(1))); in acpi_dsdt_add_gpex()
212 acpi_dsdt_add_pci_route_table(dev, cfg->irq, scope, 0); in acpi_dsdt_add_gpex()
215 aml_append(method, aml_return(aml_int(cfg->ecam.base))); in acpi_dsdt_add_gpex()
216 aml_append(dev, method); in acpi_dsdt_add_gpex()
226 0x0000, 0x0000, nr_pcie_buses - 1, 0x0000, in acpi_dsdt_add_gpex()
228 if (cfg->mmio32.size) { in acpi_dsdt_add_gpex()
230 cfg->mmio32.base, in acpi_dsdt_add_gpex()
231 cfg->mmio32.base + cfg->mmio32.size - 1); in acpi_dsdt_add_gpex()
232 for (i = 0; i < crs_range_set.mem_ranges->len; i++) { in acpi_dsdt_add_gpex()
237 entry->base, entry->limit, in acpi_dsdt_add_gpex()
238 0x0000, entry->limit - entry->base + 1)); in acpi_dsdt_add_gpex()
241 if (cfg->pio.size) { in acpi_dsdt_add_gpex()
244 cfg->pio.size - 1); in acpi_dsdt_add_gpex()
245 for (i = 0; i < crs_range_set.io_ranges->len; i++) { in acpi_dsdt_add_gpex()
249 AML_ENTIRE_RANGE, 0x0000, entry->base, in acpi_dsdt_add_gpex()
250 entry->limit, cfg->pio.base, in acpi_dsdt_add_gpex()
251 entry->limit - entry->base + 1)); in acpi_dsdt_add_gpex()
254 if (cfg->mmio64.size) { in acpi_dsdt_add_gpex()
256 cfg->mmio64.base, in acpi_dsdt_add_gpex()
257 cfg->mmio64.base + cfg->mmio64.size - 1); in acpi_dsdt_add_gpex()
258 for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) { in acpi_dsdt_add_gpex()
263 entry->base, in acpi_dsdt_add_gpex()
264 entry->limit, 0x0000, in acpi_dsdt_add_gpex()
265 entry->limit - entry->base + 1)); in acpi_dsdt_add_gpex()
268 aml_append(dev, aml_name_decl("_CRS", rbuf)); in acpi_dsdt_add_gpex()
270 acpi_dsdt_add_pci_osc(dev); in acpi_dsdt_add_gpex()
278 cfg->ecam.base, in acpi_dsdt_add_gpex()
279 cfg->ecam.base + cfg->ecam.size - 1, in acpi_dsdt_add_gpex()
281 cfg->ecam.size)); in acpi_dsdt_add_gpex()
283 aml_append(dev, dev_res0); in acpi_dsdt_add_gpex()
284 aml_append(scope, dev); in acpi_dsdt_add_gpex()
298 GPEX_HOST(obj)->gpex_cfg.irq = irq; in acpi_dsdt_add_gpex_host()
299 acpi_dsdt_add_gpex(scope, &GPEX_HOST(obj)->gpex_cfg); in acpi_dsdt_add_gpex_host()