Lines Matching +full:- +full:- +full:root
29 #include "hw/qdev-properties.h"
32 #include "hw/pci-host/designware.h"
64 * Designware has only a single root complex. Enforce the limit on the in designware_pcie_root_bus_class_init()
67 k->max_dev = 1; in designware_pcie_root_bus_class_init()
71 designware_pcie_root_to_host(DesignwarePCIERoot *root) in designware_pcie_root_to_host() argument
73 BusState *bus = qdev_get_parent_bus(DEVICE(root)); in designware_pcie_root_to_host()
74 return DESIGNWARE_PCIE_HOST(bus->parent); in designware_pcie_root_to_host()
85 * AHB/AXI bus like any other PCI-device-initiated DMA read. in designware_pcie_root_msi_read()
87 * well-behaved guests won't ever ask a PCI device to DMA from in designware_pcie_root_msi_read()
97 DesignwarePCIERoot *root = DESIGNWARE_PCIE_ROOT(opaque); in designware_pcie_root_msi_write() local
98 DesignwarePCIEHost *host = designware_pcie_root_to_host(root); in designware_pcie_root_msi_write()
100 root->msi.intr[0].status |= BIT(val) & root->msi.intr[0].enable; in designware_pcie_root_msi_write()
102 if (root->msi.intr[0].status & ~root->msi.intr[0].mask) { in designware_pcie_root_msi_write()
103 qemu_set_irq(host->pci.msi, 1); in designware_pcie_root_msi_write()
117 static void designware_pcie_root_update_msi_mapping(DesignwarePCIERoot *root) in designware_pcie_root_update_msi_mapping() argument
120 MemoryRegion *mem = &root->msi.iomem; in designware_pcie_root_update_msi_mapping()
121 const uint64_t base = root->msi.base; in designware_pcie_root_update_msi_mapping()
122 const bool enable = root->msi.intr[0].enable; in designware_pcie_root_update_msi_mapping()
129 designware_pcie_root_get_current_viewport(DesignwarePCIERoot *root) in designware_pcie_root_get_current_viewport() argument
131 const unsigned int idx = root->atu_viewport & 0xF; in designware_pcie_root_get_current_viewport()
133 !!(root->atu_viewport & DESIGNWARE_PCIE_ATU_REGION_INBOUND); in designware_pcie_root_get_current_viewport()
134 return &root->viewports[dir][idx]; in designware_pcie_root_get_current_viewport()
140 DesignwarePCIERoot *root = DESIGNWARE_PCIE_ROOT(d); in designware_pcie_root_config_read() local
142 designware_pcie_root_get_current_viewport(root); in designware_pcie_root_config_read()
167 val = extract64(root->msi.base, in designware_pcie_root_config_read()
172 val = root->msi.intr[0].enable; in designware_pcie_root_config_read()
176 val = root->msi.intr[0].mask; in designware_pcie_root_config_read()
180 val = root->msi.intr[0].status; in designware_pcie_root_config_read()
188 val = root->atu_viewport; in designware_pcie_root_config_read()
193 val = extract64(viewport->base, in designware_pcie_root_config_read()
199 val = extract64(viewport->target, in designware_pcie_root_config_read()
205 val = viewport->limit; in designware_pcie_root_config_read()
210 val = viewport->cr[(address - DESIGNWARE_PCIE_ATU_CR1) / in designware_pcie_root_config_read()
226 DesignwarePCIERoot *root = viewport->root; in designware_pcie_root_data_access() local
228 const uint8_t busnum = DESIGNWARE_PCIE_ATU_BUS(viewport->target); in designware_pcie_root_data_access()
229 const uint8_t devfn = DESIGNWARE_PCIE_ATU_DEVFN(viewport->target); in designware_pcie_root_data_access()
230 PCIBus *pcibus = pci_get_bus(PCI_DEVICE(root)); in designware_pcie_root_data_access()
234 addr &= pci_config_size(pcidev) - 1; in designware_pcie_root_data_access()
272 static void designware_pcie_update_viewport(DesignwarePCIERoot *root, in designware_pcie_update_viewport() argument
275 const uint64_t target = viewport->target; in designware_pcie_update_viewport()
276 const uint64_t base = viewport->base; in designware_pcie_update_viewport()
277 const uint64_t size = (uint64_t)viewport->limit - base + 1; in designware_pcie_update_viewport()
278 const bool enabled = viewport->cr[1] & DESIGNWARE_PCIE_ATU_ENABLE; in designware_pcie_update_viewport()
282 if (viewport->cr[0] == DESIGNWARE_PCIE_ATU_TYPE_MEM) { in designware_pcie_update_viewport()
283 current = &viewport->mem; in designware_pcie_update_viewport()
284 other = &viewport->cfg; in designware_pcie_update_viewport()
287 current = &viewport->cfg; in designware_pcie_update_viewport()
288 other = &viewport->mem; in designware_pcie_update_viewport()
307 DesignwarePCIERoot *root = DESIGNWARE_PCIE_ROOT(d); in designware_pcie_root_config_write() local
308 DesignwarePCIEHost *host = designware_pcie_root_to_host(root); in designware_pcie_root_config_write()
310 designware_pcie_root_get_current_viewport(root); in designware_pcie_root_config_write()
316 /* No-op */ in designware_pcie_root_config_write()
321 root->msi.base = deposit64(root->msi.base, in designware_pcie_root_config_write()
324 designware_pcie_root_update_msi_mapping(root); in designware_pcie_root_config_write()
328 root->msi.intr[0].enable = val; in designware_pcie_root_config_write()
329 designware_pcie_root_update_msi_mapping(root); in designware_pcie_root_config_write()
333 root->msi.intr[0].mask = val; in designware_pcie_root_config_write()
337 root->msi.intr[0].status ^= val; in designware_pcie_root_config_write()
338 if (!root->msi.intr[0].status) { in designware_pcie_root_config_write()
339 qemu_set_irq(host->pci.msi, 0); in designware_pcie_root_config_write()
345 (DESIGNWARE_PCIE_NUM_VIEWPORTS - 1); in designware_pcie_root_config_write()
346 root->atu_viewport = val; in designware_pcie_root_config_write()
351 viewport->base = deposit64(viewport->base, in designware_pcie_root_config_write()
358 viewport->target = deposit64(viewport->target, in designware_pcie_root_config_write()
364 viewport->limit = val; in designware_pcie_root_config_write()
368 viewport->cr[0] = val; in designware_pcie_root_config_write()
371 viewport->cr[1] = val; in designware_pcie_root_config_write()
372 designware_pcie_update_viewport(root, viewport); in designware_pcie_root_config_write()
391 DesignwarePCIERoot *root = DESIGNWARE_PCIE_ROOT(dev); in designware_pcie_root_realize() local
392 DesignwarePCIEHost *host = designware_pcie_root_to_host(root); in designware_pcie_root_realize()
394 MemoryRegion *address_space = &host->pci.memory; in designware_pcie_root_realize()
405 br->bus_name = "dw-pcie"; in designware_pcie_root_realize()
407 pci_set_word(dev->config + PCI_COMMAND, in designware_pcie_root_realize()
410 pci_config_set_interrupt_pin(dev->config, 1); in designware_pcie_root_realize()
426 viewport = &root->viewports[DESIGNWARE_PCIE_VIEWPORT_INBOUND][i]; in designware_pcie_root_realize()
427 viewport->inbound = true; in designware_pcie_root_realize()
428 viewport->base = 0x0000000000000000ULL; in designware_pcie_root_realize()
429 viewport->target = 0x0000000000000000ULL; in designware_pcie_root_realize()
430 viewport->limit = UINT32_MAX; in designware_pcie_root_realize()
431 viewport->cr[0] = DESIGNWARE_PCIE_ATU_TYPE_MEM; in designware_pcie_root_realize()
433 source = &host->pci.address_space_root; in designware_pcie_root_realize()
438 * Configure MemoryRegion implementing PCI -> CPU memory in designware_pcie_root_realize()
441 mem = &viewport->mem; in designware_pcie_root_realize()
443 memory_region_init_alias(mem, OBJECT(root), name, destination, in designware_pcie_root_realize()
445 memory_region_add_subregion_overlap(source, dummy_offset, mem, -1); in designware_pcie_root_realize()
449 viewport = &root->viewports[DESIGNWARE_PCIE_VIEWPORT_OUTBOUND][i]; in designware_pcie_root_realize()
450 viewport->root = root; in designware_pcie_root_realize()
451 viewport->inbound = false; in designware_pcie_root_realize()
452 viewport->base = 0x0000000000000000ULL; in designware_pcie_root_realize()
453 viewport->target = 0x0000000000000000ULL; in designware_pcie_root_realize()
454 viewport->limit = UINT32_MAX; in designware_pcie_root_realize()
455 viewport->cr[0] = DESIGNWARE_PCIE_ATU_TYPE_MEM; in designware_pcie_root_realize()
457 destination = &host->pci.memory; in designware_pcie_root_realize()
462 * Configure MemoryRegion implementing CPU -> PCI memory in designware_pcie_root_realize()
465 mem = &viewport->mem; in designware_pcie_root_realize()
467 memory_region_init_alias(mem, OBJECT(root), name, destination, in designware_pcie_root_realize()
477 mem = &viewport->cfg; in designware_pcie_root_realize()
479 memory_region_init_io(&viewport->cfg, OBJECT(root), in designware_pcie_root_realize()
496 viewport = &root->viewports[DESIGNWARE_PCIE_VIEWPORT_INBOUND][0]; in designware_pcie_root_realize()
497 viewport->cr[1] = DESIGNWARE_PCIE_ATU_ENABLE; in designware_pcie_root_realize()
498 designware_pcie_update_viewport(root, viewport); in designware_pcie_root_realize()
500 memory_region_init_io(&root->msi.iomem, OBJECT(root), in designware_pcie_root_realize()
502 root, "pcie-msi", 0x4); in designware_pcie_root_realize()
509 memory_region_add_subregion(address_space, dummy_offset, &root->msi.iomem); in designware_pcie_root_realize()
510 memory_region_set_enabled(&root->msi.iomem, false); in designware_pcie_root_realize()
517 qemu_set_irq(host->pci.irqs[irq_num], level); in designware_pcie_set_irq()
527 .name = "designware-pcie-msi-bank",
539 .name = "designware-pcie-msi",
555 .name = "designware-pcie-viewport",
568 .name = "designware-pcie-root",
596 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); in designware_pcie_root_class_init()
598 k->vendor_id = PCI_VENDOR_ID_SYNOPSYS; in designware_pcie_root_class_init()
599 k->device_id = 0xABCD; in designware_pcie_root_class_init()
600 k->revision = 0; in designware_pcie_root_class_init()
601 k->class_id = PCI_CLASS_BRIDGE_PCI; in designware_pcie_root_class_init()
602 k->exit = pci_bridge_exitfn; in designware_pcie_root_class_init()
603 k->realize = designware_pcie_root_realize; in designware_pcie_root_class_init()
604 k->config_read = designware_pcie_root_config_read; in designware_pcie_root_class_init()
605 k->config_write = designware_pcie_root_config_write; in designware_pcie_root_class_init()
609 * PCI-facing part of the host bridge, not usable without the in designware_pcie_root_class_init()
610 * host-facing part, which can't be device_add'ed, yet. in designware_pcie_root_class_init()
612 dc->user_creatable = false; in designware_pcie_root_class_init()
613 dc->vmsd = &vmstate_designware_pcie_root; in designware_pcie_root_class_init()
620 PCIDevice *device = pci_find_device(pci->bus, 0, 0); in designware_pcie_host_mmio_read()
632 PCIDevice *device = pci_find_device(pci->bus, 0, 0); in designware_pcie_host_mmio_write()
662 return &s->pci.address_space; in designware_pcie_host_set_iommu()
676 for (i = 0; i < ARRAY_SIZE(s->pci.irqs); i++) { in designware_pcie_host_realize()
677 sysbus_init_irq(sbd, &s->pci.irqs[i]); in designware_pcie_host_realize()
679 sysbus_init_irq(sbd, &s->pci.msi); in designware_pcie_host_realize()
681 memory_region_init_io(&s->mmio, in designware_pcie_host_realize()
686 sysbus_init_mmio(sbd, &s->mmio); in designware_pcie_host_realize()
688 memory_region_init(&s->pci.io, OBJECT(s), "pcie-pio", 16); in designware_pcie_host_realize()
689 memory_region_init(&s->pci.memory, OBJECT(s), in designware_pcie_host_realize()
690 "pcie-bus-memory", in designware_pcie_host_realize()
693 pci->bus = pci_register_root_bus(dev, "pcie", in designware_pcie_host_realize()
697 &s->pci.memory, in designware_pcie_host_realize()
698 &s->pci.io, in designware_pcie_host_realize()
701 pci->bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE; in designware_pcie_host_realize()
703 memory_region_init(&s->pci.address_space_root, in designware_pcie_host_realize()
705 "pcie-bus-address-space-root", in designware_pcie_host_realize()
707 memory_region_add_subregion(&s->pci.address_space_root, in designware_pcie_host_realize()
708 0x0, &s->pci.memory); in designware_pcie_host_realize()
709 address_space_init(&s->pci.address_space, in designware_pcie_host_realize()
710 &s->pci.address_space_root, in designware_pcie_host_realize()
711 "pcie-bus-address-space"); in designware_pcie_host_realize()
712 pci_setup_iommu(pci->bus, &designware_iommu_ops, s); in designware_pcie_host_realize()
714 qdev_realize(DEVICE(&s->root), BUS(pci->bus), &error_fatal); in designware_pcie_host_realize()
718 .name = "designware-pcie-host",
722 VMSTATE_STRUCT(root,
737 hc->root_bus_path = designware_pcie_host_root_bus_path; in designware_pcie_host_class_init()
738 dc->realize = designware_pcie_host_realize; in designware_pcie_host_class_init()
739 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); in designware_pcie_host_class_init()
740 dc->fw_name = "pci"; in designware_pcie_host_class_init()
741 dc->vmsd = &vmstate_designware_pcie_host; in designware_pcie_host_class_init()
747 DesignwarePCIERoot *root = &s->root; in designware_pcie_host_init() local
749 object_initialize_child(obj, "root", root, TYPE_DESIGNWARE_PCIE_ROOT); in designware_pcie_host_init()
750 qdev_prop_set_int32(DEVICE(root), "addr", PCI_DEVFN(0, 0)); in designware_pcie_host_init()
751 qdev_prop_set_bit(DEVICE(root), "multifunction", false); in designware_pcie_host_init()