9  * Most of the code was migrated from hw/pci-bridge/ioh3420.
12  * See the COPYING file in the top-level directory.
19 #include "hw/qdev-properties.h"
21 static void rp_aer_vector_update(PCIDevice *d)  in rp_aer_vector_update()  argument
23     PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(d);  in rp_aer_vector_update()
25     if (rpc->aer_vector) {  in rp_aer_vector_update()
26         pcie_aer_root_set_vector(d, rpc->aer_vector(d));  in rp_aer_vector_update()
30 static void rp_write_config(PCIDevice *d, uint32_t address,  in rp_write_config()  argument
34         pci_get_long(d->config + d->exp.aer_cap + PCI_ERR_ROOT_COMMAND);  in rp_write_config()
37     pcie_cap_slot_get(d, &slt_ctl, &slt_sta);  in rp_write_config()
39     pci_bridge_write_config(d, address, val, len);  in rp_write_config()
40     rp_aer_vector_update(d);  in rp_write_config()
41     pcie_cap_slot_write_config(d, slt_ctl, slt_sta, address, val, len);  in rp_write_config()
42     pcie_aer_write_config(d, address, val, len);  in rp_write_config()
43     pcie_aer_root_write_config(d, address, val, len, root_cmd);  in rp_write_config()
48     PCIDevice *d = PCI_DEVICE(obj);  in rp_reset_hold()  local
51     rp_aer_vector_update(d);  in rp_reset_hold()
52     pcie_cap_root_reset(d);  in rp_reset_hold()
53     pcie_cap_deverr_reset(d);  in rp_reset_hold()
54     pcie_cap_slot_reset(d);  in rp_reset_hold()
55     pcie_cap_arifwd_reset(d);  in rp_reset_hold()
56     pcie_acs_reset(d);  in rp_reset_hold()
57     pcie_aer_root_reset(d);  in rp_reset_hold()
59     pci_bridge_disable_base_limit(d);  in rp_reset_hold()
62 static void rp_realize(PCIDevice *d, Error **errp)  in rp_realize()  argument
64     PCIEPort *p = PCIE_PORT(d);  in rp_realize()
65     PCIESlot *s = PCIE_SLOT(d);  in rp_realize()
66     PCIDeviceClass *dc = PCI_DEVICE_GET_CLASS(d);  in rp_realize()
67     PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(d);  in rp_realize()
70     pci_config_set_interrupt_pin(d->config, 1);  in rp_realize()
71     if (d->cap_present & QEMU_PCIE_CAP_CXL) {  in rp_realize()
72         pci_bridge_initfn(d, TYPE_CXL_BUS);  in rp_realize()
74         pci_bridge_initfn(d, TYPE_PCIE_BUS);  in rp_realize()
76     pcie_port_init_reg(d);  in rp_realize()
78     rc = pci_bridge_ssvid_init(d, rpc->ssvid_offset, dc->vendor_id,  in rp_realize()
79                                rpc->ssid, errp);  in rp_realize()
81         error_append_hint(errp, "Can't init SSV ID, error %d\n", rc);  in rp_realize()
85     if (rpc->interrupts_init) {  in rp_realize()
86         rc = rpc->interrupts_init(d, errp);  in rp_realize()
92     rc = pcie_cap_init(d, rpc->exp_offset, PCI_EXP_TYPE_ROOT_PORT,  in rp_realize()
93                        p->port, errp);  in rp_realize()
96                           "error %d\n", rc);  in rp_realize()
100     pcie_cap_arifwd_init(d);  in rp_realize()
101     pcie_cap_deverr_init(d);  in rp_realize()
102     pcie_cap_slot_init(d, s);  in rp_realize()
103     pcie_cap_root_init(d);  in rp_realize()
105     pcie_chassis_create(s->chassis);  in rp_realize()
108         error_setg(errp, "Can't add chassis slot, error %d", rc);  in rp_realize()
112     rc = pcie_aer_init(d, PCI_ERR_VER, rpc->aer_offset,  in rp_realize()
117     pcie_aer_root_init(d);  in rp_realize()
118     rp_aer_vector_update(d);  in rp_realize()
120     if (rpc->acs_offset && !s->disable_acs) {  in rp_realize()
121         pcie_acs_init(d, rpc->acs_offset);  in rp_realize()
128     pcie_cap_exit(d);  in rp_realize()
130     if (rpc->interrupts_uninit) {  in rp_realize()
131         rpc->interrupts_uninit(d);  in rp_realize()
134     pci_bridge_exitfn(d);  in rp_realize()
137 static void rp_exit(PCIDevice *d)  in rp_exit()  argument
139     PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(d);  in rp_exit()
140     PCIESlot *s = PCIE_SLOT(d);  in rp_exit()
142     pcie_aer_exit(d);  in rp_exit()
144     pcie_cap_exit(d);  in rp_exit()
145     if (rpc->interrupts_uninit) {  in rp_exit()
146         rpc->interrupts_uninit(d);  in rp_exit()
148     pci_bridge_exitfn(d);  in rp_exit()
154     DEFINE_PROP_BOOL("disable-acs", PCIESlot, disable_acs, false),
161     if (!s->speed) {  in rp_instance_post_init()
162         s->speed = QEMU_PCI_EXP_LNK_2_5GT;  in rp_instance_post_init()
165     if (!s->width) {  in rp_instance_post_init()
166         s->width = QEMU_PCI_EXP_LNK_X1;  in rp_instance_post_init()
176     k->config_write = rp_write_config;  in rp_class_init()
177     k->realize = rp_realize;  in rp_class_init()
178     k->exit = rp_exit;  in rp_class_init()
179     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);  in rp_class_init()
180     rc->phases.hold = rp_reset_hold;  in rp_class_init()