9  * This work is licensed under the terms of the GNU GPL, version 2 or later.
10  * See the COPYING file in the top-level directory.
18 #include "hw/qdev-properties.h"
19 #include "hw/qdev-properties-system.h"
23 #define TYPE_GEN_PCIE_ROOT_PORT                "pcie-root-port"
56         assert(rc == -ENOTSUP);  in gen_rp_interrupts_init()
73     return rp->migrate_msix;  in gen_rp_test_migrate_msix()
84     rpc->parent_realize(dev, &local_err);  in gen_rp_realize()
91      * reserving IO space led to worse issues in 6.1, when this hunk was  in gen_rp_realize()
95     if (s->hide_native_hotplug_cap && grp->res_reserve.io == -1 && s->hotplug) {  in gen_rp_realize()
96         grp->res_reserve.io = GEN_PCIE_ROOT_DEFAULT_IO_RANGE;  in gen_rp_realize()
99                                               grp->res_reserve, errp);  in gen_rp_realize()
102         rpc->parent_class.exit(d);  in gen_rp_realize()
106     if (!grp->res_reserve.io) {  in gen_rp_realize()
107         pci_word_test_and_clear_mask(d->wmask + PCI_COMMAND,  in gen_rp_realize()
109         d->wmask[PCI_IO_BASE] = 0;  in gen_rp_realize()
110         d->wmask[PCI_IO_LIMIT] = 0;  in gen_rp_realize()
115     .name = "pcie-root-port",
132     DEFINE_PROP_BOOL("x-migrate-msix", GenPCIERootPort,
134     DEFINE_PROP_UINT32("bus-reserve", GenPCIERootPort,
135                        res_reserve.bus, -1),
136     DEFINE_PROP_SIZE("io-reserve", GenPCIERootPort,
137                      res_reserve.io, -1),
138     DEFINE_PROP_SIZE("mem-reserve", GenPCIERootPort,
139                      res_reserve.mem_non_pref, -1),
140     DEFINE_PROP_SIZE("pref32-reserve", GenPCIERootPort,
141                      res_reserve.mem_pref_32, -1),
142     DEFINE_PROP_SIZE("pref64-reserve", GenPCIERootPort,
143                      res_reserve.mem_pref_64, -1),
144     DEFINE_PROP_PCIE_LINK_SPEED("x-speed", PCIESlot,
146     DEFINE_PROP_PCIE_LINK_WIDTH("x-width", PCIESlot,
156     k->vendor_id = PCI_VENDOR_ID_REDHAT;  in gen_rp_dev_class_init()
157     k->device_id = PCI_DEVICE_ID_REDHAT_PCIE_RP;  in gen_rp_dev_class_init()
158     dc->desc = "PCI Express Root Port";  in gen_rp_dev_class_init()
159     dc->vmsd = &vmstate_rp_dev;  in gen_rp_dev_class_init()
162     device_class_set_parent_realize(dc, gen_rp_realize, &rpc->parent_realize);  in gen_rp_dev_class_init()
164     rpc->aer_vector = gen_rp_aer_vector;  in gen_rp_dev_class_init()
165     rpc->interrupts_init = gen_rp_interrupts_init;  in gen_rp_dev_class_init()
166     rpc->interrupts_uninit = gen_rp_interrupts_uninit;  in gen_rp_dev_class_init()
167     rpc->aer_offset = GEN_PCIE_ROOT_PORT_AER_OFFSET;  in gen_rp_dev_class_init()
168     rpc->acs_offset = GEN_PCIE_ROOT_PORT_ACS_OFFSET;  in gen_rp_dev_class_init()