8  * SPDX-License-Identifier: GPL-2.0-or-later
13 #include "hw/qdev-properties.h"
14 #include "hw/qdev-properties-system.h"
18 #include "hw/pci-bridge/cxl_upstream_port.h"
37     return &usp->cxl_cstate;  in cxl_usp_to_cstate()
45     if (range_contains(&usp->cxl_cstate.dvsecs[EXTENSIONS_PORT_DVSEC], addr)) {  in cxl_usp_dvsec_write_config()
46         uint8_t *reg = &dev->config[addr];  in cxl_usp_dvsec_write_config()
47         addr -= usp->cxl_cstate.dvsecs[EXTENSIONS_PORT_DVSEC].lob;  in cxl_usp_dvsec_write_config()
67     pcie_doe_write_config(&usp->doe_cdat, address, val, len);  in cxl_usp_write_config()
80     if (pcie_doe_read_config(&usp->doe_cdat, address, len, &val)) {  in cxl_usp_read_config()
89     uint32_t *reg_state = usp->cxl_cstate.crb.cache_mem_registers;  in latch_registers()
90     uint32_t *write_msk = usp->cxl_cstate.crb.cache_mem_regs_write_mask;  in latch_registers()
104     pcie_cap_fill_link_ep_usp(d, usp->width, usp->speed);  in cxl_usp_reset()
120         .cap                     = 0x27, /* Cache, IO, Mem, non-MLD */  in build_dvsecs()
121         .ctrl                    = 0x27, /* Cache, IO, Mem */  in build_dvsecs()
142     CDATObject *cdat = &CXL_USP(doe_cap->pdev)->cxl_cstate.cdat;  in cxl_doe_cdat_rsp()
149     cxl_doe_cdat_update(&CXL_USP(doe_cap->pdev)->cxl_cstate, &error_fatal);  in cxl_doe_cdat_rsp()
150     assert(cdat->entry_len);  in cxl_doe_cdat_rsp()
158     ent = req->entry_handle;  in cxl_doe_cdat_rsp()
159     base = cdat->entry[ent].base;  in cxl_doe_cdat_rsp()
160     len = cdat->entry[ent].length;  in cxl_doe_cdat_rsp()
171         .entry_handle = (ent < cdat->entry_len - 1) ?  in cxl_doe_cdat_rsp()
175     memcpy(doe_cap->read_mbox, &rsp, sizeof(rsp));  in cxl_doe_cdat_rsp()
176         memcpy(doe_cap->read_mbox + DIV_ROUND_UP(sizeof(rsp), sizeof(uint32_t)),  in cxl_doe_cdat_rsp()
179     doe_cap->read_mbox_len += rsp.header.length;  in cxl_doe_cdat_rsp()
200     PCIBus *bus = &PCI_BRIDGE(us)->sec_bus;  in build_cdat_table()
205     for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {  in build_cdat_table()
206         PCIDevice *d = bus->devices[devfn];  in build_cdat_table()
209         if (!d || !pci_is_express(d) || !d->exp.exp_cap) {  in build_cdat_table()
222         port_ids[count] = port->port;  in build_cdat_table()
226     /* May not yet have any ports - try again later */  in build_cdat_table()
231     sslbis_size = sizeof(CDATSslbis) + sizeof(*sslbis_latency->sslbe) * count;  in build_cdat_table()
245         sslbis_latency->sslbe[i] = (CDATSslbe) {  in build_cdat_table()
265         sslbis_bandwidth->sslbe[i] = (CDATSslbe) {  in build_cdat_table()
297     CXLComponentState *cxl_cstate = &usp->cxl_cstate;  in cxl_usp_realize()
298     ComponentRegisters *cregs = &cxl_cstate->crb;  in cxl_usp_realize()
299     MemoryRegion *component_bar = &cregs->component_registers;  in cxl_usp_realize()
308         assert(rc == -ENOTSUP);  in cxl_usp_realize()
313                        PCI_EXP_TYPE_UPSTREAM, p->port, errp);  in cxl_usp_realize()
325     if (usp->sn != UI64_NULL) {  in cxl_usp_realize()
326         pcie_dev_ser_num_init(d, CXL_UPSTREAM_PORT_SN_OFFSET, usp->sn);  in cxl_usp_realize()
328     cxl_cstate->dvsec_offset = CXL_UPSTREAM_PORT_DVSEC_OFFSET;  in cxl_usp_realize()
329     cxl_cstate->pdev = d;  in cxl_usp_realize()
337     pcie_doe_init(d, &usp->doe_cdat, cxl_cstate->dvsec_offset, doe_cdat_prot,  in cxl_usp_realize()
340     cxl_cstate->cdat.build_cdat_table = build_cdat_table;  in cxl_usp_realize()
341     cxl_cstate->cdat.free_cdat_table = free_default_cdat_table;  in cxl_usp_realize()
342     cxl_cstate->cdat.private = d;  in cxl_usp_realize()
368     DEFINE_PROP_PCIE_LINK_SPEED("x-speed", CXLUpstreamPort,
370     DEFINE_PROP_PCIE_LINK_WIDTH("x-width", CXLUpstreamPort,
371                                 width, PCIE_LINK_WIDTH_16),
379     k->config_write = cxl_usp_write_config;  in cxl_upstream_class_init()
380     k->config_read = cxl_usp_read_config;  in cxl_upstream_class_init()
381     k->realize = cxl_usp_realize;  in cxl_upstream_class_init()
382     k->exit = cxl_usp_exitfn;  in cxl_upstream_class_init()
383     k->vendor_id = 0x19e5; /* Huawei */  in cxl_upstream_class_init()
384     k->device_id = 0xa128; /* Emulated CXL Switch Upstream Port */  in cxl_upstream_class_init()
385     k->revision = 0;  in cxl_upstream_class_init()
386     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);  in cxl_upstream_class_init()
387     dc->desc = "CXL Switch Upstream Port";  in cxl_upstream_class_init()