Lines Matching refs:pmr

539     if (!n->pmr.cmse) {  in nvme_addr_is_pmr()
543 hi = n->pmr.cba + int128_get64(n->pmr.dev->mr.size); in nvme_addr_is_pmr()
545 return addr >= n->pmr.cba && addr < hi; in nvme_addr_is_pmr()
550 return memory_region_get_ram_ptr(&n->pmr.dev->mr) + (addr - n->pmr.cba); in nvme_addr_to_pmr()
829 bool cmb = false, pmr = false; in nvme_map_addr() local
844 pmr = true; in nvme_map_addr()
847 if (cmb || pmr) { in nvme_map_addr()
7674 if (n->pmr.dev) { in nvme_ctrl_shutdown()
7675 memory_region_msync(&n->pmr.dev->mr, 0, n->pmr.dev->size); in nvme_ctrl_shutdown()
7972 memory_region_set_enabled(&n->pmr.dev->mr, true); in nvme_write_bar()
7975 memory_region_set_enabled(&n->pmr.dev->mr, false); in nvme_write_bar()
7977 n->pmr.cmse = false; in nvme_write_bar()
7999 n->pmr.cmse = false; in nvme_write_bar()
8005 if (cba + int128_get64(n->pmr.dev->mr.size) < cba) { in nvme_write_bar()
8011 n->pmr.cmse = true; in nvme_write_bar()
8012 n->pmr.cba = cba; in nvme_write_bar()
8072 memory_region_msync(&n->pmr.dev->mr, 0, n->pmr.dev->size); in nvme_mmio_read()
8318 if (n->pmr.dev) { in nvme_check_params()
8324 if (host_memory_backend_is_mapped(n->pmr.dev)) { in nvme_check_params()
8326 object_get_canonical_path_component(OBJECT(n->pmr.dev))); in nvme_check_params()
8330 if (!is_power_of_2(n->pmr.dev->size)) { in nvme_check_params()
8335 host_memory_backend_set_mapped(n->pmr.dev, true); in nvme_check_params()
8360 if (n->pmr.dev) { in nvme_check_params()
8543 PCI_BASE_ADDRESS_MEM_PREFETCH, &n->pmr.dev->mr); in nvme_init_pmr()
8545 memory_region_set_enabled(&n->pmr.dev->mr, false); in nvme_init_pmr()
8753 if (n->pmr.dev) { in nvme_init_pci()
8901 NVME_CAP_SET_PMRS(cap, n->pmr.dev ? 1 : 0); in nvme_init_ctrl()
9035 if (n->pmr.dev) { in nvme_exit()
9036 host_memory_backend_set_mapped(n->pmr.dev, false); in nvme_exit()
9054 DEFINE_PROP_LINK("pmrdev", NvmeCtrl, pmr.dev, TYPE_MEMORY_BACKEND,