Lines Matching full:port
97 unsigned int port_index; /* dual port RAM index */
101 XlnxXpsEthLitePort port[2]; member
107 if (s->port[0].reg.tx_gie & GIE_GIE) { in eth_pulse_irq()
119 return memory_region_get_ram_ptr(&s->port[port_index].txbuf); in txbuf_ptr()
124 return memory_region_get_ram_ptr(&s->port[port_index].rxbuf); in rxbuf_ptr()
135 r = s->port[port_index].reg.tx_len; in port_tx_read()
138 r = s->port[port_index].reg.tx_gie; in port_tx_read()
141 r = s->port[port_index].reg.tx_ctrl; in port_tx_read()
158 s->port[port_index].reg.tx_len = value; in port_tx_write()
161 s->port[port_index].reg.tx_gie = value; in port_tx_write()
167 s->port[port_index].reg.tx_len); in port_tx_write()
168 if (s->port[port_index].reg.tx_ctrl & CTRL_I) { in port_tx_write()
173 if (s->port[port_index].reg.tx_ctrl & CTRL_I) { in port_tx_write()
181 s->port[port_index].reg.tx_ctrl = value & ~(CTRL_P | CTRL_S); in port_tx_write()
213 r = s->port[port_index].reg.rx_ctrl; in port_rx_read()
233 s->port[port_index].reg.rx_ctrl = value; in port_rx_write()
261 return !(s->port[s->port_index].reg.rx_ctrl & CTRL_S); in eth_can_rx()
273 if (s->port[port_index].reg.rx_ctrl & CTRL_S) { in eth_rx()
274 trace_ethlite_pkt_lost(s->port[port_index].reg.rx_ctrl); in eth_rx()
284 s->port[port_index].reg.rx_ctrl |= CTRL_S; in eth_rx()
285 if (s->port[port_index].reg.rx_ctrl & CTRL_I) { in eth_rx()
342 memory_region_init_ram(&s->port[i].txbuf, OBJECT(dev), in xilinx_ethlite_realize()
345 memory_region_add_subregion(&s->container, 0x0800 * i, &s->port[i].txbuf); in xilinx_ethlite_realize()
346 memory_region_init_io(&s->port[i].txio, OBJECT(dev), in xilinx_ethlite_realize()
351 &s->port[i].txio); in xilinx_ethlite_realize()
353 memory_region_init_ram(&s->port[i].rxbuf, OBJECT(dev), in xilinx_ethlite_realize()
357 &s->port[i].rxbuf); in xilinx_ethlite_realize()
358 memory_region_init_io(&s->port[i].rxio, OBJECT(dev), in xilinx_ethlite_realize()
363 &s->port[i].rxio); in xilinx_ethlite_realize()