132                                      hwaddr pa,  in DECLARE_CLASS_CHECKERS()
137     ring->pa = pa;  in DECLARE_CLASS_CHECKERS()
144         vmw_shmem_set(d, pa, 0, size * cell_size);  in DECLARE_CLASS_CHECKERS()
151           (r)->pa, (r)->size, (r)->cell_size, (r)->gen, (r)->next)
171     return ring->pa + ring->next * ring->cell_size;  in vmxnet3_ring_curr_cell_pa()
957 vmxnet3_pci_dma_write_rxcd(PCIDevice *pcidev, dma_addr_t pa,  in vmxnet3_pci_dma_write_rxcd()  argument
963     pci_dma_write(pcidev, pa, rxcd, sizeof(*rxcd));  in vmxnet3_pci_dma_write_rxcd()
1400     uint64_t pa;  in vmxnet3_activate_device()  local
1478         pa = VMXNET3_READ_TX_QUEUE_DESCR64(d, qdescr_pa, conf.txRingBasePA);  in vmxnet3_activate_device()
1484         vmxnet3_ring_init(d, &s->txq_descr[i].tx_ring, pa, size,  in vmxnet3_activate_device()
1491         pa = VMXNET3_READ_TX_QUEUE_DESCR64(d, qdescr_pa, conf.compRingBasePA);  in vmxnet3_activate_device()
1496         vmxnet3_ring_init(d, &s->txq_descr[i].comp_ring, pa, size,  in vmxnet3_activate_device()
1534             pa = VMXNET3_READ_RX_QUEUE_DESCR64(d, qd_pa, conf.rxRingBasePA[j]);  in vmxnet3_activate_device()
1539             vmxnet3_ring_init(d, &s->rxq_descr[i].rx_ring[j], pa, size,  in vmxnet3_activate_device()
1542                       i, j, pa, size);  in vmxnet3_activate_device()
1546         pa = VMXNET3_READ_RX_QUEUE_DESCR64(d, qd_pa, conf.compRingBasePA);  in vmxnet3_activate_device()
1551         vmxnet3_ring_init(d, &s->rxq_descr[i].comp_ring, pa, size,  in vmxnet3_activate_device()
1553         VMW_CFPRN("RXC queue %d: Base: %" PRIx64 ", Size: %d", i, pa, size);  in vmxnet3_activate_device()
2307         VMSTATE_UINT64(pa, Vmxnet3Ring),