Lines Matching +full:len +full:- +full:or +full:- +full:define
4 * Copyright (c) 2017 Mark Cave-Ayland
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 #include "hw/qdev-properties.h"
38 #define HME_REG_SIZE 0x8000
40 #define HME_SEB_REG_SIZE 0x2000
42 #define HME_SEBI_RESET 0x0
43 #define HME_SEB_RESET_ETX 0x1
44 #define HME_SEB_RESET_ERX 0x2
46 #define HME_SEBI_STAT 0x100
47 #define HME_SEBI_STAT_LINUXBUG 0x108
48 #define HME_SEB_STAT_RXTOHOST 0x10000
49 #define HME_SEB_STAT_NORXD 0x20000
50 #define HME_SEB_STAT_MIFIRQ 0x800000
51 #define HME_SEB_STAT_HOSTTOTX 0x1000000
52 #define HME_SEB_STAT_TXALL 0x2000000
54 #define HME_SEBI_IMASK 0x104
55 #define HME_SEBI_IMASK_LINUXBUG 0x10c
57 #define HME_ETX_REG_SIZE 0x2000
59 #define HME_ETXI_PENDING 0x0
61 #define HME_ETXI_RING 0x8
62 #define HME_ETXI_RING_ADDR 0xffffff00
63 #define HME_ETXI_RING_OFFSET 0xff
65 #define HME_ETXI_RSIZE 0x2c
67 #define HME_ERX_REG_SIZE 0x2000
69 #define HME_ERXI_CFG 0x0
70 #define HME_ERX_CFG_RINGSIZE 0x600
71 #define HME_ERX_CFG_RINGSIZE_SHIFT 9
72 #define HME_ERX_CFG_BYTEOFFSET 0x38
73 #define HME_ERX_CFG_BYTEOFFSET_SHIFT 3
74 #define HME_ERX_CFG_CSUMSTART 0x7f0000
75 #define HME_ERX_CFG_CSUMSHIFT 16
77 #define HME_ERXI_RING 0x4
78 #define HME_ERXI_RING_ADDR 0xffffff00
79 #define HME_ERXI_RING_OFFSET 0xff
81 #define HME_MAC_REG_SIZE 0x1000
83 #define HME_MACI_TXCFG 0x20c
84 #define HME_MAC_TXCFG_ENABLE 0x1
86 #define HME_MACI_RXCFG 0x30c
87 #define HME_MAC_RXCFG_ENABLE 0x1
88 #define HME_MAC_RXCFG_PMISC 0x40
89 #define HME_MAC_RXCFG_HENABLE 0x800
91 #define HME_MACI_MACADDR2 0x318
92 #define HME_MACI_MACADDR1 0x31c
93 #define HME_MACI_MACADDR0 0x320
95 #define HME_MACI_HASHTAB3 0x340
96 #define HME_MACI_HASHTAB2 0x344
97 #define HME_MACI_HASHTAB1 0x348
98 #define HME_MACI_HASHTAB0 0x34c
100 #define HME_MIF_REG_SIZE 0x20
102 #define HME_MIFI_FO 0xc
103 #define HME_MIF_FO_ST 0xc0000000
104 #define HME_MIF_FO_ST_SHIFT 30
105 #define HME_MIF_FO_OPC 0x30000000
106 #define HME_MIF_FO_OPC_SHIFT 28
107 #define HME_MIF_FO_PHYAD 0x0f800000
108 #define HME_MIF_FO_PHYAD_SHIFT 23
109 #define HME_MIF_FO_REGAD 0x007c0000
110 #define HME_MIF_FO_REGAD_SHIFT 18
111 #define HME_MIF_FO_TAMSB 0x20000
112 #define HME_MIF_FO_TALSB 0x10000
113 #define HME_MIF_FO_DATA 0xffff
115 #define HME_MIFI_CFG 0x10
116 #define HME_MIF_CFG_MDI0 0x100
117 #define HME_MIF_CFG_MDI1 0x200
119 #define HME_MIFI_IMASK 0x14
121 #define HME_MIFI_STAT 0x18
125 #define HME_PHYAD_INTERNAL 1
126 #define HME_PHYAD_EXTERNAL 0
128 #define MII_COMMAND_START 0x1
129 #define MII_COMMAND_READ 0x2
130 #define MII_COMMAND_WRITE 0x1
132 #define TYPE_SUNHME "sunhme"
136 #define HME_FIFO_SIZE 0x800
139 #define HME_DESC_SIZE 0x8
141 #define HME_XD_OWN 0x80000000
142 #define HME_XD_OFL 0x40000000
143 #define HME_XD_SOP 0x40000000
144 #define HME_XD_EOP 0x20000000
145 #define HME_XD_RXLENMSK 0x3fff0000
146 #define HME_XD_RXLENSHIFT 16
147 #define HME_XD_RXCKSUM 0xffff
148 #define HME_XD_TXLENMSK 0x00001fff
149 #define HME_XD_TXCKSUM 0x10000000
150 #define HME_XD_TXCSSTUFF 0xff00000
151 #define HME_XD_TXCSSTUFFSHIFT 20
152 #define HME_XD_TXCSSTART 0xfc000
153 #define HME_XD_TXCSSTARTSHIFT 14
155 #define HME_MII_REGS_SIZE 0x20
187 s->sebregs[HME_SEBI_RESET] &= ~HME_SEB_RESET_ETX; in sunhme_reset_tx()
193 s->sebregs[HME_SEBI_RESET] &= ~HME_SEB_RESET_ERX; in sunhme_reset_rx()
201 /* MIF interrupt mask (16-bit) */ in sunhme_update_irq()
202 uint32_t mifmask = ~(s->mifregs[HME_MIFI_IMASK >> 2]) & 0xffff; in sunhme_update_irq()
203 uint32_t mif = s->mifregs[HME_MIFI_STAT >> 2] & mifmask; in sunhme_update_irq()
206 uint32_t sebmask = ~(s->sebregs[HME_SEBI_IMASK >> 2]) & in sunhme_update_irq()
208 uint32_t seb = s->sebregs[HME_SEBI_STAT >> 2] & sebmask; in sunhme_update_irq()
247 val = s->sebregs[HME_SEBI_RESET >> 2]; in sunhme_seb_write()
251 s->sebregs[addr >> 2] = val; in sunhme_seb_write()
273 val = s->sebregs[addr >> 2]; in sunhme_seb_read()
278 s->sebregs[HME_SEBI_STAT >> 2] &= HME_SEB_STAT_MIFIRQ; in sunhme_seb_read()
315 s->etxregs[addr >> 2] = val; in sunhme_etx_write()
324 val = s->etxregs[addr >> 2]; in sunhme_etx_read()
348 s->erxregs[addr >> 2] = val; in sunhme_erx_write()
357 val = s->erxregs[addr >> 2]; in sunhme_erx_read()
378 uint64_t oldval = s->macregs[addr >> 2]; in sunhme_mac_write()
382 s->macregs[addr >> 2] = val; in sunhme_mac_write()
388 qemu_flush_queued_packets(qemu_get_queue(s->nic)); in sunhme_mac_write()
400 val = s->macregs[addr >> 2]; in sunhme_mac_read()
433 s->miiregs[MII_BMSR] |= MII_BMSR_AN_COMP; in sunhme_mii_write()
435 if (!qemu_get_queue(s->nic)->link_down) { in sunhme_mii_write()
436 s->miiregs[MII_ANLPAR] |= MII_ANLPAR_TXFD; in sunhme_mii_write()
437 s->miiregs[MII_BMSR] |= MII_BMSR_LINK_ST; in sunhme_mii_write()
443 s->miiregs[reg] = data; in sunhme_mii_write()
448 uint16_t data = s->miiregs[reg]; in sunhme_mii_read()
466 /* Mask the read-only bits */ in sunhme_mif_write()
468 val |= s->mifregs[HME_MIFI_CFG >> 2] & in sunhme_mif_write()
505 s->mifregs[addr >> 2] = val; in sunhme_mif_write()
514 val = s->mifregs[addr >> 2]; in sunhme_mif_read()
519 s->mifregs[HME_MIFI_STAT >> 2] = 0; in sunhme_mif_read()
541 qemu_send_packet(qemu_get_queue(s->nic), buf, size); in sunhme_transmit_frame()
546 return (s->etxregs[HME_ETXI_RSIZE >> 2] + 1) << 4; in sunhme_get_tx_ring_count()
551 return s->etxregs[HME_ETXI_RING >> 2] & HME_ETXI_RING_OFFSET; in sunhme_get_tx_ring_nr()
556 uint32_t ring = s->etxregs[HME_ETXI_RING >> 2] & ~HME_ETXI_RING_OFFSET; in sunhme_set_tx_ring_nr()
559 s->etxregs[HME_ETXI_RING >> 2] = ring; in sunhme_set_tx_ring_nr()
567 int cr, nr, len, xmit_pos, csum_offset = 0, csum_stuff_offset = 0; in sunhme_transmit() local
571 tb = s->etxregs[HME_ETXI_RING >> 2] & HME_ETXI_RING_ADDR; in sunhme_transmit()
584 len = status & HME_XD_TXLENMSK; in sunhme_transmit()
586 if (xmit_pos + len > HME_FIFO_SIZE) { in sunhme_transmit()
587 len = HME_FIFO_SIZE - xmit_pos; in sunhme_transmit()
590 pci_dma_read(d, addr, &xmit_buffer[xmit_pos], len); in sunhme_transmit()
591 xmit_pos += len; in sunhme_transmit()
603 if (xmit_pos - len <= csum_offset && xmit_pos > csum_offset) { in sunhme_transmit()
604 sum += net_checksum_add(xmit_pos - csum_offset, in sunhme_transmit()
606 trace_sunhme_tx_xsum_add(csum_offset, xmit_pos - csum_offset); in sunhme_transmit()
608 sum += net_checksum_add(len, xmit_buffer + xmit_pos - len); in sunhme_transmit()
609 trace_sunhme_tx_xsum_add(xmit_pos - len, len); in sunhme_transmit()
622 if (s->macregs[HME_MACI_TXCFG >> 2] & HME_MAC_TXCFG_ENABLE) { in sunhme_transmit()
643 intstatus = s->sebregs[HME_SEBI_STAT >> 2]; in sunhme_transmit()
645 s->sebregs[HME_SEBI_STAT >> 2] = intstatus; in sunhme_transmit()
648 s->etxregs[HME_ETXI_PENDING >> 2] = 0; in sunhme_transmit()
654 intstatus = s->sebregs[HME_SEBI_STAT >> 2]; in sunhme_transmit()
656 s->sebregs[HME_SEBI_STAT >> 2] = intstatus; in sunhme_transmit()
664 return !!(s->macregs[HME_MACI_RXCFG >> 2] & HME_MAC_RXCFG_ENABLE); in sunhme_can_receive()
671 if (nc->link_down) { in sunhme_link_status_changed()
672 s->miiregs[MII_ANLPAR] &= ~MII_ANLPAR_TXFD; in sunhme_link_status_changed()
673 s->miiregs[MII_BMSR] &= ~MII_BMSR_LINK_ST; in sunhme_link_status_changed()
675 s->miiregs[MII_ANLPAR] |= MII_ANLPAR_TXFD; in sunhme_link_status_changed()
676 s->miiregs[MII_BMSR] |= MII_BMSR_LINK_ST; in sunhme_link_status_changed()
680 s->mifregs[HME_MIFI_STAT >> 2] = 0xffff; in sunhme_link_status_changed()
686 uint32_t rings = (s->erxregs[HME_ERXI_CFG >> 2] & HME_ERX_CFG_RINGSIZE) in sunhme_get_rx_ring_count()
705 return s->erxregs[HME_ERXI_RING >> 2] & HME_ERXI_RING_OFFSET; in sunhme_get_rx_ring_nr()
710 uint32_t ring = s->erxregs[HME_ERXI_RING >> 2] & ~HME_ERXI_RING_OFFSET; in sunhme_set_rx_ring_nr()
713 s->erxregs[HME_ERXI_RING >> 2] = ring; in sunhme_set_rx_ring_nr()
724 int nr, cr, len, rxoffset, csum_offset; in sunhme_receive() local
729 if (!(s->macregs[HME_MACI_RXCFG >> 2] & HME_MAC_RXCFG_ENABLE)) { in sunhme_receive()
737 if (!(s->macregs[HME_MACI_RXCFG >> 2] & HME_MAC_RXCFG_PMISC)) { in sunhme_receive()
739 if (((s->macregs[HME_MACI_MACADDR0 >> 2] & 0xff00) >> 8) == buf[0] && in sunhme_receive()
740 (s->macregs[HME_MACI_MACADDR0 >> 2] & 0xff) == buf[1] && in sunhme_receive()
741 ((s->macregs[HME_MACI_MACADDR1 >> 2] & 0xff00) >> 8) == buf[2] && in sunhme_receive()
742 (s->macregs[HME_MACI_MACADDR1 >> 2] & 0xff) == buf[3] && in sunhme_receive()
743 ((s->macregs[HME_MACI_MACADDR2 >> 2] & 0xff00) >> 8) == buf[4] && in sunhme_receive()
744 (s->macregs[HME_MACI_MACADDR2 >> 2] & 0xff) == buf[5]) { in sunhme_receive()
751 } else if (s->macregs[HME_MACI_RXCFG >> 2] & HME_MAC_RXCFG_HENABLE) { in sunhme_receive()
754 if (!(s->macregs[(HME_MACI_HASHTAB0 >> 2) - (mcast_idx >> 4)] & in sunhme_receive()
759 return -1; in sunhme_receive()
766 return -1; in sunhme_receive()
774 rb = s->erxregs[HME_ERXI_RING >> 2] & HME_ERXI_RING_ADDR; in sunhme_receive()
783 s->sebregs[HME_SEBI_STAT >> 2] |= HME_SEB_STAT_NORXD; in sunhme_receive()
786 return -1; in sunhme_receive()
789 rxoffset = (s->erxregs[HME_ERXI_CFG >> 2] & HME_ERX_CFG_BYTEOFFSET) >> in sunhme_receive()
796 len = size; in sunhme_receive()
799 len = buffersize; in sunhme_receive()
802 pci_dma_write(d, addr, buf, len); in sunhme_receive()
804 trace_sunhme_rx_desc(buffer, rxoffset, status, len, cr, nr); in sunhme_receive()
807 csum_offset = (s->erxregs[HME_ERXI_CFG >> 2] & HME_ERX_CFG_CSUMSTART) >> in sunhme_receive()
810 sum += net_checksum_add(len - csum_offset, (uint8_t *)buf + csum_offset); in sunhme_receive()
818 status |= len << HME_XD_RXLENSHIFT; in sunhme_receive()
832 intstatus = s->sebregs[HME_SEBI_STAT >> 2]; in sunhme_receive()
834 s->sebregs[HME_SEBI_STAT >> 2] = intstatus; in sunhme_receive()
838 return len; in sunhme_receive()
855 pci_conf = pci_dev->config; in sunhme_realize()
858 memory_region_init(&s->hme, OBJECT(pci_dev), "sunhme", HME_REG_SIZE); in sunhme_realize()
859 pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->hme); in sunhme_realize()
861 memory_region_init_io(&s->sebreg, OBJECT(pci_dev), &sunhme_seb_ops, s, in sunhme_realize()
863 memory_region_add_subregion(&s->hme, 0, &s->sebreg); in sunhme_realize()
865 memory_region_init_io(&s->etxreg, OBJECT(pci_dev), &sunhme_etx_ops, s, in sunhme_realize()
867 memory_region_add_subregion(&s->hme, 0x2000, &s->etxreg); in sunhme_realize()
869 memory_region_init_io(&s->erxreg, OBJECT(pci_dev), &sunhme_erx_ops, s, in sunhme_realize()
871 memory_region_add_subregion(&s->hme, 0x4000, &s->erxreg); in sunhme_realize()
873 memory_region_init_io(&s->macreg, OBJECT(pci_dev), &sunhme_mac_ops, s, in sunhme_realize()
875 memory_region_add_subregion(&s->hme, 0x6000, &s->macreg); in sunhme_realize()
877 memory_region_init_io(&s->mifreg, OBJECT(pci_dev), &sunhme_mif_ops, s, in sunhme_realize()
879 memory_region_add_subregion(&s->hme, 0x7000, &s->mifreg); in sunhme_realize()
881 qemu_macaddr_default_if_unset(&s->conf.macaddr); in sunhme_realize()
882 s->nic = qemu_new_nic(&net_sunhme_info, &s->conf, in sunhme_realize()
883 object_get_typename(OBJECT(d)), d->id, in sunhme_realize()
884 &d->mem_reentrancy_guard, s); in sunhme_realize()
885 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); in sunhme_realize()
892 device_add_bootindex_property(obj, &s->conf.bootindex, in sunhme_instance_init()
893 "bootindex", "/ethernet-phy@0", in sunhme_instance_init()
902 s->mifregs[HME_MIFI_CFG >> 2] |= HME_MIF_CFG_MDI0; in sunhme_reset()
905 s->miiregs[MII_ANAR] = MII_ANAR_TXFD; in sunhme_reset()
906 s->miiregs[MII_BMSR] = MII_BMSR_AUTONEG | MII_BMSR_100TX_FD | in sunhme_reset()
909 if (!qemu_get_queue(s->nic)->link_down) { in sunhme_reset()
910 s->miiregs[MII_ANLPAR] |= MII_ANLPAR_TXFD; in sunhme_reset()
911 s->miiregs[MII_BMSR] |= MII_BMSR_LINK_ST; in sunhme_reset()
915 s->miiregs[MII_PHYID1] = DP83840_PHYID1; in sunhme_reset()
916 s->miiregs[MII_PHYID2] = DP83840_PHYID2; in sunhme_reset()
919 s->mifregs[HME_MIFI_IMASK >> 2] = 0xffff; in sunhme_reset()
920 s->sebregs[HME_SEBI_IMASK >> 2] = 0xff7fffff; in sunhme_reset()
945 k->realize = sunhme_realize; in sunhme_class_init()
946 k->vendor_id = PCI_VENDOR_ID_SUN; in sunhme_class_init()
947 k->device_id = PCI_DEVICE_ID_SUN_HME; in sunhme_class_init()
948 k->class_id = PCI_CLASS_NETWORK_ETHERNET; in sunhme_class_init()
949 dc->vmsd = &vmstate_hme; in sunhme_class_init()
952 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); in sunhme_class_init()