Lines Matching +full:remove +full:- +full:item
17 #include "hw/qdev-properties.h"
29 * and control byte (per figure 8-1 in the Microchip Technology
147 if (s->tx_fifo_len == 0) in smc91c111_update()
148 s->int_level |= INT_TX_EMPTY; in smc91c111_update()
149 if (s->tx_fifo_done_len != 0) in smc91c111_update()
150 s->int_level |= INT_TX; in smc91c111_update()
151 level = (s->int_level & s->int_mask) != 0; in smc91c111_update()
152 qemu_set_irq(s->irq, level); in smc91c111_update()
157 if ((s->rcr & RCR_RXEN) == 0 || (s->rcr & RCR_SOFT_RST)) { in smc91c111_can_receive()
160 if (s->allocated == (1 << NUM_PACKETS) - 1 || in smc91c111_can_receive()
161 s->rx_fifo_len == NUM_PACKETS) { in smc91c111_can_receive()
170 qemu_flush_queued_packets(qemu_get_queue(s->nic)); in smc91c111_flush_queued_packets()
178 if (s->allocated == (1 << NUM_PACKETS) - 1) { in smc91c111_allocate_packet()
183 if ((s->allocated & (1 << i)) == 0) in smc91c111_allocate_packet()
186 s->allocated |= 1 << i; in smc91c111_allocate_packet()
194 s->tx_alloc = smc91c111_allocate_packet(s); in smc91c111_tx_alloc()
195 if (s->tx_alloc == 0x80) in smc91c111_tx_alloc()
197 s->int_level |= INT_ALLOC; in smc91c111_tx_alloc()
201 /* Remove and item from the RX FIFO. */
206 if (s->rx_fifo_len == 0) { in smc91c111_pop_rx_fifo()
215 s->rx_fifo_len--; in smc91c111_pop_rx_fifo()
216 if (s->rx_fifo_len) { in smc91c111_pop_rx_fifo()
217 for (i = 0; i < s->rx_fifo_len; i++) in smc91c111_pop_rx_fifo()
218 s->rx_fifo[i] = s->rx_fifo[i + 1]; in smc91c111_pop_rx_fifo()
219 s->int_level |= INT_RCV; in smc91c111_pop_rx_fifo()
221 s->int_level &= ~INT_RCV; in smc91c111_pop_rx_fifo()
227 /* Remove an item from the TX completion FIFO. */
232 if (s->tx_fifo_done_len == 0) in smc91c111_pop_tx_fifo_done()
234 s->tx_fifo_done_len--; in smc91c111_pop_tx_fifo_done()
235 for (i = 0; i < s->tx_fifo_done_len; i++) in smc91c111_pop_tx_fifo_done()
236 s->tx_fifo_done[i] = s->tx_fifo_done[i + 1]; in smc91c111_pop_tx_fifo_done()
253 s->allocated &= ~(1 << packet); in smc91c111_release_packet()
254 if (s->tx_alloc == 0x80) in smc91c111_release_packet()
261 if (s->ctr & CTR_AUTO_RELEASE) { in smc91c111_complete_tx_packet()
264 } else if (s->tx_fifo_done_len < NUM_PACKETS) { in smc91c111_complete_tx_packet()
265 s->tx_fifo_done[s->tx_fifo_done_len++] = packetnum; in smc91c111_complete_tx_packet()
278 if ((s->tcr & TCR_TXEN) == 0) in smc91c111_do_tx()
280 if (s->tx_fifo_len == 0) in smc91c111_do_tx()
282 for (i = 0; i < s->tx_fifo_len; i++) { in smc91c111_do_tx()
283 packetnum = s->tx_fifo[i]; in smc91c111_do_tx()
286 p = &s->data[packetnum][0]; in smc91c111_do_tx()
303 len -= 6; in smc91c111_do_tx()
309 if (len < 64 && (s->tcr & TCR_PAD_EN)) { in smc91c111_do_tx()
310 memset(p + len, 0, 64 - len); in smc91c111_do_tx()
321 add_crc = (control & 0x10) || (s->tcr & TCR_NOCRC) == 0; in smc91c111_do_tx()
332 qemu_send_packet(qemu_get_queue(s->nic), p, len); in smc91c111_do_tx()
334 s->tx_fifo_len = 0; in smc91c111_do_tx()
352 if (s->tx_fifo_len == NUM_PACKETS) in smc91c111_queue_tx()
354 s->tx_fifo[s->tx_fifo_len++] = packet; in smc91c111_queue_tx()
362 s->bank = 0; in smc91c111_reset()
363 s->tx_fifo_len = 0; in smc91c111_reset()
364 s->tx_fifo_done_len = 0; in smc91c111_reset()
365 s->rx_fifo_len = 0; in smc91c111_reset()
366 s->allocated = 0; in smc91c111_reset()
367 s->packet_num = 0; in smc91c111_reset()
368 s->tx_alloc = 0; in smc91c111_reset()
369 s->tcr = 0; in smc91c111_reset()
370 s->rcr = 0; in smc91c111_reset()
371 s->cr = 0xa0b1; in smc91c111_reset()
372 s->ctr = 0x1210; in smc91c111_reset()
373 s->ptr = 0; in smc91c111_reset()
374 s->ercv = 0x1f; in smc91c111_reset()
375 s->int_level = INT_TX_EMPTY; in smc91c111_reset()
376 s->int_mask = 0; in smc91c111_reset()
380 #define SET_LOW(name, val) s->name = (s->name & 0xff00) | val
381 #define SET_HIGH(name, val) s->name = (s->name & 0xff) | (val << 8)
385 * indexes a 2048-byte data frame). Add the specified offset to it,
392 return (s->ptr + offset) & R_PTR_PTR_MASK; in ptr_reg_add()
399 * guarantees to return an in-bounds offset.
405 if (s->ptr & R_PTR_AUTOINCR_MASK) { in data_reg_ptr()
410 p = FIELD_EX32(s->ptr, PTR, PTR); in data_reg_ptr()
411 s->ptr = FIELD_DP32(s->ptr, PTR, PTR, ptr_reg_add(s, 1)); in data_reg_ptr()
433 s->bank = value; in smc91c111_writeb()
438 switch (s->bank) { in smc91c111_writeb()
452 if (s->rcr & RCR_SOFT_RST) { in smc91c111_writeb()
505 case 0: /* no-op */ in smc91c111_writeb()
508 s->tx_alloc = 0x80; in smc91c111_writeb()
509 s->int_level &= ~INT_ALLOC; in smc91c111_writeb()
514 s->allocated = 0; in smc91c111_writeb()
515 s->tx_fifo_len = 0; in smc91c111_writeb()
516 s->tx_fifo_done_len = 0; in smc91c111_writeb()
517 s->rx_fifo_len = 0; in smc91c111_writeb()
518 s->tx_alloc = 0; in smc91c111_writeb()
520 case 3: /* Remove from RX FIFO. */ in smc91c111_writeb()
523 case 4: /* Remove from RX FIFO and release. */ in smc91c111_writeb()
524 if (s->rx_fifo_len > 0) { in smc91c111_writeb()
525 smc91c111_release_packet(s, s->rx_fifo[0]); in smc91c111_writeb()
530 smc91c111_release_packet(s, s->packet_num); in smc91c111_writeb()
533 smc91c111_queue_tx(s, s->packet_num); in smc91c111_writeb()
536 s->tx_fifo_len = 0; in smc91c111_writeb()
537 s->tx_fifo_done_len = 0; in smc91c111_writeb()
545 s->packet_num = value; in smc91c111_writeb()
561 if (s->ptr & 0x8000) in smc91c111_writeb()
562 n = s->rx_fifo[0]; in smc91c111_writeb()
564 n = s->packet_num; in smc91c111_writeb()
573 s->data[n][p] = value; in smc91c111_writeb()
577 s->int_level &= ~(value & 0xd6); in smc91c111_writeb()
583 s->int_mask = value; in smc91c111_writeb()
599 s->ercv = value & 0x1f; in smc91c111_writeb()
609 s->bank, offset, value); in smc91c111_writeb()
618 return s->bank; in smc91c111_readb()
622 switch (s->bank) { in smc91c111_readb()
626 return s->tcr & 0xff; in smc91c111_readb()
628 return s->tcr >> 8; in smc91c111_readb()
634 return s->rcr & 0xff; in smc91c111_readb()
636 return s->rcr >> 8; in smc91c111_readb()
649 if (s->allocated & (1 << i)) in smc91c111_readb()
665 return s->cr & 0xff; in smc91c111_readb()
667 return s->cr >> 8; in smc91c111_readb()
672 return s->conf.macaddr.a[offset - 4]; in smc91c111_readb()
674 return s->gpr & 0xff; in smc91c111_readb()
676 return s->gpr >> 8; in smc91c111_readb()
678 return s->ctr & 0xff; in smc91c111_readb()
680 return s->ctr >> 8; in smc91c111_readb()
689 return s->packet_num; in smc91c111_readb()
691 return s->tx_alloc; in smc91c111_readb()
693 if (s->tx_fifo_done_len == 0) in smc91c111_readb()
696 return s->tx_fifo_done[0]; in smc91c111_readb()
698 if (s->rx_fifo_len == 0) in smc91c111_readb()
701 return s->rx_fifo[0]; in smc91c111_readb()
703 return s->ptr & 0xff; in smc91c111_readb()
705 return (s->ptr >> 8) & 0xf7; in smc91c111_readb()
711 if (s->ptr & 0x8000) in smc91c111_readb()
712 n = s->rx_fifo[0]; in smc91c111_readb()
714 n = s->packet_num; in smc91c111_readb()
723 return s->data[n][p]; in smc91c111_readb()
726 return s->int_level; in smc91c111_readb()
728 return s->int_mask; in smc91c111_readb()
748 return s->ercv; in smc91c111_readb()
756 s->bank, offset); in smc91c111_readb()
776 /* 32-bit writes to offset 0xc only actually write to the bank select in smc91c111_writefn()
805 if ((s->rcr & RCR_RXEN) == 0 || (s->rcr & RCR_SOFT_RST)) in smc91c111_receive()
806 return -1; in smc91c111_receive()
814 crc = (s->rcr & RCR_STRIP_CRC) == 0; in smc91c111_receive()
819 return -1; in smc91c111_receive()
823 return -1; in smc91c111_receive()
824 s->rx_fifo[s->rx_fifo_len++] = packetnum; in smc91c111_receive()
828 p = &s->data[packetnum][0]; in smc91c111_receive()
846 *(p++) = buf[size - 1]; in smc91c111_receive()
847 pad = 64 - size; in smc91c111_receive()
854 The pictures in the documentation show the CRC aligned on a 16-bit in smc91c111_receive()
864 *(p++) = buf[size - 1]; in smc91c111_receive()
871 s->int_level |= INT_RCV; in smc91c111_receive()
900 memory_region_init_io(&s->mmio, OBJECT(s), &smc91c111_mem_ops, s, in smc91c111_realize()
901 "smc91c111-mmio", 16); in smc91c111_realize()
902 sysbus_init_mmio(sbd, &s->mmio); in smc91c111_realize()
903 sysbus_init_irq(sbd, &s->irq); in smc91c111_realize()
904 qemu_macaddr_default_if_unset(&s->conf.macaddr); in smc91c111_realize()
905 s->nic = qemu_new_nic(&net_smc91c111_info, &s->conf, in smc91c111_realize()
906 object_get_typename(OBJECT(dev)), dev->id, in smc91c111_realize()
907 &dev->mem_reentrancy_guard, s); in smc91c111_realize()
908 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); in smc91c111_realize()
920 dc->realize = smc91c111_realize; in smc91c111_class_init()
922 dc->vmsd = &vmstate_smc91c111; in smc91c111_class_init()