Lines Matching +full:led +full:- +full:2
4 Copyright(c) 1999 - 2006 Intel Corporation.
8 version 2, as published by the Free Software Foundation.
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
37 #define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */
38 #define E1000_EIAC 0x000DC /* Ext. Interrupt Auto Clear - RW */
39 #define E1000_IVAR 0x000E4 /* Interrupt Vector Allocation Register - RW */
40 #define E1000_EITR 0x000E8 /* Extended Interrupt Throttling Rate - RW */
41 #define E1000_RDBAL1 0x02900 /* RX Descriptor Base Address Low (1) - RW */
42 #define E1000_RDBAH1 0x02904 /* RX Descriptor Base Address High (1) - RW */
43 #define E1000_RDLEN1 0x02908 /* RX Descriptor Length (1) - RW */
44 #define E1000_RDH1 0x02910 /* RX Descriptor Head (1) - RW */
45 #define E1000_RDT1 0x02918 /* RX Descriptor Tail (1) - RW */
46 #define E1000_FCRTV 0x05F40 /* Flow Control Refresh Timer Value - RW */
47 #define E1000_TXCW 0x00178 /* TX Configuration Word - RW */
48 #define E1000_RXCW 0x00180 /* RX Configuration Word - RO */
49 #define E1000_TBT 0x00448 /* TX Burst Timer - RW */
50 #define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */
54 #define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */
55 #define E1000_PBM 0x10000 /* Packet Buffer Memory - RW */
56 #define E1000_PBS 0x01008 /* Packet Buffer Size - RW */
58 #define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */
63 #define E1000_ERT 0x02008 /* Early Rx Threshold - RW */
65 #define E1000_PSRCTL 0x02170 /* Packet Split Receive Control - RW */
66 #define E1000_RDBAL 0x02800 /* RX Descriptor Base Address Low - RW */
67 #define E1000_RDBAH 0x02804 /* RX Descriptor Base Address High - RW */
68 #define E1000_RDLEN 0x02808 /* RX Descriptor Length - RW */
69 #define E1000_RDH 0x02810 /* RX Descriptor Head - RW */
70 #define E1000_RDT 0x02818 /* RX Descriptor Tail - RW */
71 #define E1000_RDTR 0x02820 /* RX Delay Timer - RW */
73 #define E1000_RDBAL0 E1000_RDBAL /* RX Desc Base Address Low (0) - RW */
75 #define E1000_RDBAH0 E1000_RDBAH /* RX Desc Base Address High (0) - RW */
77 #define E1000_RDLEN0 E1000_RDLEN /* RX Desc Length (0) - RW */
79 #define E1000_RDH0 E1000_RDH /* RX Desc Head (0) - RW */
81 #define E1000_RDT0 E1000_RDT /* RX Desc Tail (0) - RW */
83 #define E1000_RDTR0 E1000_RDTR /* RX Delay Timer (0) - RW */
84 #define E1000_RXDCTL 0x02828 /* RX Descriptor Control queue 0 - RW */
85 #define E1000_RXDCTL1 0x02928 /* RX Descriptor Control queue 1 - RW */
86 #define E1000_RADV 0x0282C /* RX Interrupt Absolute Delay Timer - RW */
87 #define E1000_RSRPD 0x02C00 /* RX Small Packet Detect - RW */
88 #define E1000_RAID 0x02C08 /* Receive Ack Interrupt Delay - RW */
89 #define E1000_POEMB 0x00F10 /* PHY OEM Bits Register - RW */
90 #define E1000_TDBAL 0x03800 /* TX Descriptor Base Address Low - RW */
92 #define E1000_TDBAH 0x03804 /* TX Descriptor Base Address High - RW */
94 #define E1000_TDLEN 0x03808 /* TX Descriptor Length - RW */
96 #define E1000_TDH 0x03810 /* TX Descriptor Head - RW */
98 #define E1000_TDT 0x03818 /* TX Descripotr Tail - RW */
100 #define E1000_TIDV 0x03820 /* TX Interrupt Delay Value - RW */
102 #define E1000_TXDCTL 0x03828 /* TX Descriptor Control - RW */
103 #define E1000_TADV 0x0382C /* TX Interrupt Absolute Delay Val - RW */
104 #define E1000_TSPMT 0x03830 /* TCP Segmentation PAD & Min Threshold - RW */
106 #define E1000_TDBAL1 0x03900 /* TX Desc Base Address Low (1) - RW */
107 #define E1000_TDBAH1 0x03904 /* TX Desc Base Address High (1) - RW */
108 #define E1000_TDLEN1 0x03908 /* TX Desc Length (1) - RW */
109 #define E1000_TDH1 0x03910 /* TX Desc Head (1) - RW */
110 #define E1000_TDT1 0x03918 /* TX Desc Tail (1) - RW */
111 #define E1000_TXDCTL1 0x03928 /* TX Descriptor Control (1) - RW */
113 #define E1000_SEQEC 0x04038 /* Sequence Error Count - R/clr */
114 #define E1000_CEXTERR 0x0403C /* Carrier Extension Error Count - R/clr */
115 #define E1000_TSCTFC 0x040FC /* TCP Segmentation Context TX Fail - R/clr */
122 #define E1000_MFUTP01 0x05828 /* Management Flex UDP/TCP Ports 0/1 - RW */
123 #define E1000_MFUTP23 0x05830 /* Management Flex UDP/TCP Ports 2/3 - RW */
124 #define E1000_FFLT 0x05F00 /* Flexible Filter Length Table - RW Array */
126 #define E1000_FFVT 0x09800 /* Flexible Filter Value Table - RW Array */
128 #define E1000_KUMCTRLSTA 0x00034 /* MAC-PHY interface - RW */
129 #define E1000_MDPHYA 0x0003C /* PHY address - RW */
131 #define E1000_GCR2 0x05B64 /* 3GIO Control Register 2 */
135 #define E1000_RXMTRL 0x0B634 /* Time sync Rx EtherType and Msg Type - RW */
136 #define E1000_RXUDP 0x0B638 /* Time Sync Rx UDP Port - RW */
137 #define E1000_RXCFGL 0x0B634 /* RX Ethertype and Message Type - RW*/
141 #define E1000_CPUVEC 0x02C10 /* CPU Vector Register - RW */
148 #define E1000_XDBAL_MASK (~(BIT(4) - 1))
149 #define E1000_XDLEN_MASK ((BIT(20) - 1) & (~(BIT(7) - 1)))
192 /* 82574-specific registers */
196 #define PHY_COPPER_STAT2 0x13 /* Copper Specific Status Register 2 */
198 #define PHY_COPPER_CTRL2 0x1A /* Copper Specific Control Register 2 */
205 /* 82574-specific registers - page 2 */
209 #define PHY_MAC_CTRL2 0x15 /* MAC Specific Control Register 2 */
211 /* 82574-specific registers - page 3 */
212 #define PHY_LED_03_FUNC_CTRL1 0x10 /* LED[3:0] Function Control */
213 #define PHY_LED_03_POL_CTRL 0x11 /* LED[3:0] Polarity Control */
214 #define PHY_LED_TIMER_CTRL 0x12 /* LED Timer Control */
215 #define PHY_LED_45_CTRL 0x13 /* LED[5:4] Function Control and Polarity */
217 /* 82574-specific registers - page 5 */
218 #define PHY_1000T_SKEW 0x14 /* 1000 BASE - T Pair Skew Register */
219 #define PHY_1000T_SWAP 0x15 /* 1000 BASE - T Pair Swap and Polarity */
221 /* 82574-specific registers - page 6 */
226 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
244 #define E1000_STATUS_FUNC_SHIFT 2
260 #define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */
261 #define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */