Lines Matching refs:E1000State
140 typedef struct E1000State_st E1000State; typedef
152 DECLARE_OBJ_CHECKERS(E1000State, E1000BaseClass, in DECLARE_OBJ_CHECKERS() argument
157 e1000_link_up(E1000State *s) in DECLARE_OBJ_CHECKERS()
166 e1000_autoneg_done(E1000State *s) in e1000_autoneg_done()
175 have_autoneg(E1000State *s) in have_autoneg()
181 set_phy_ctrl(E1000State *s, int index, uint16_t val) in set_phy_ctrl()
198 static void (*phyreg_writeops[])(E1000State *, int, uint16_t) = {
273 set_interrupt_cause(E1000State *s, int index, uint32_t val) in set_interrupt_cause()
342 E1000State *s = opaque; in e1000_mit_timer()
350 set_ics(E1000State *s, int index, uint32_t val) in set_ics()
360 E1000State *s = opaque; in e1000_autoneg_timer()
369 E1000State *s = opaque; in e1000_vet_init_need()
376 E1000State *d = E1000(obj); in e1000_reset_hold()
406 set_ctrl(E1000State *s, int index, uint32_t val) in set_ctrl()
415 E1000State *s = opaque; in e1000_flush_queue_timer()
421 set_rx_control(E1000State *s, int index, uint32_t val) in set_rx_control()
433 set_mdic(E1000State *s, int index, uint32_t val) in set_mdic()
468 get_eecd(E1000State *s, int index) in get_eecd()
482 set_eecd(E1000State *s, int index, uint32_t val) in set_eecd()
518 flash_eerd_read(E1000State *s, int x) in flash_eerd_read()
546 inc_tx_bcast_or_mcast_count(E1000State *s, const unsigned char *arr) in inc_tx_bcast_or_mcast_count()
556 e1000_send_packet(E1000State *s, const uint8_t *buf, int size) in e1000_send_packet()
572 xmit_seg(E1000State *s) in xmit_seg()
638 process_tx_desc(E1000State *s, struct e1000_tx_desc *dp) in process_tx_desc()
728 txdesc_writeback(E1000State *s, dma_addr_t base, struct e1000_tx_desc *dp) in txdesc_writeback()
743 static uint64_t tx_desc_base(E1000State *s) in tx_desc_base()
752 start_xmit(E1000State *s) in start_xmit()
800 receive_filter(E1000State *s, const void *buf) in receive_filter()
810 E1000State *s = qemu_get_nic_opaque(nc); in e1000_set_link_status()
828 static bool e1000_has_rxbufs(E1000State *s, size_t total_size) in e1000_has_rxbufs()
849 E1000State *s = qemu_get_nic_opaque(nc); in e1000_can_receive()
855 static uint64_t rx_desc_base(E1000State *s) in rx_desc_base()
864 e1000_receiver_overrun(E1000State *s, size_t size) in e1000_receiver_overrun()
875 E1000State *s = qemu_get_nic_opaque(nc); in e1000_receive_iov()
1024 mac_readreg(E1000State *s, int index) in mac_readreg()
1030 mac_icr_read(E1000State *s, int index) in mac_icr_read()
1040 mac_read_clr4(E1000State *s, int index) in mac_read_clr4()
1049 mac_read_clr8(E1000State *s, int index) in mac_read_clr8()
1059 mac_writereg(E1000State *s, int index, uint32_t val) in mac_writereg()
1073 set_rdt(E1000State *s, int index, uint32_t val) in set_rdt()
1083 set_##num##bit(E1000State *s, int index, uint32_t val) \
1094 set_dlen(E1000State *s, int index, uint32_t val) in set_dlen()
1100 set_tctl(E1000State *s, int index, uint32_t val) in set_tctl()
1108 set_icr(E1000State *s, int index, uint32_t val) in set_icr()
1115 set_imc(E1000State *s, int index, uint32_t val) in set_imc()
1122 set_ims(E1000State *s, int index, uint32_t val) in set_ims()
1129 typedef uint32_t (*readops)(E1000State *, int);
1180 typedef void (*writeops)(E1000State *, int, uint32_t);
1264 E1000State *s = opaque; in e1000_mmio_write()
1291 E1000State *s = opaque; in e1000_mmio_read()
1325 E1000State *s = opaque; in e1000_io_read()
1334 E1000State *s = opaque; in e1000_io_write()
1352 E1000State *s = opaque; in e1000_pre_save()
1383 E1000State *s = opaque; in e1000_post_load()
1414 E1000State *s = opaque; in e1000_tx_tso_post_load()
1421 E1000State *s = opaque; in e1000_tso_state_needed()
1431 VMSTATE_UINT32(mac_reg[RDTR], E1000State),
1432 VMSTATE_UINT32(mac_reg[RADV], E1000State),
1433 VMSTATE_UINT32(mac_reg[TADV], E1000State),
1434 VMSTATE_UINT32(mac_reg[ITR], E1000State),
1435 VMSTATE_BOOL(mit_irq_level, E1000State),
1445 VMSTATE_UINT32_ARRAY(mac_reg, E1000State, 0x8000),
1457 VMSTATE_UINT8(tx.tso_props.ipcss, E1000State),
1458 VMSTATE_UINT8(tx.tso_props.ipcso, E1000State),
1459 VMSTATE_UINT16(tx.tso_props.ipcse, E1000State),
1460 VMSTATE_UINT8(tx.tso_props.tucss, E1000State),
1461 VMSTATE_UINT8(tx.tso_props.tucso, E1000State),
1462 VMSTATE_UINT16(tx.tso_props.tucse, E1000State),
1463 VMSTATE_UINT32(tx.tso_props.paylen, E1000State),
1464 VMSTATE_UINT8(tx.tso_props.hdr_len, E1000State),
1465 VMSTATE_UINT16(tx.tso_props.mss, E1000State),
1466 VMSTATE_INT8(tx.tso_props.ip, E1000State),
1467 VMSTATE_INT8(tx.tso_props.tcp, E1000State),
1479 VMSTATE_PCI_DEVICE(parent_obj, E1000State),
1482 VMSTATE_UINT32(rxbuf_size, E1000State),
1483 VMSTATE_UINT32(rxbuf_min_shift, E1000State),
1484 VMSTATE_UINT32(eecd_state.val_in, E1000State),
1485 VMSTATE_UINT16(eecd_state.bitnum_in, E1000State),
1486 VMSTATE_UINT16(eecd_state.bitnum_out, E1000State),
1487 VMSTATE_UINT16(eecd_state.reading, E1000State),
1488 VMSTATE_UINT32(eecd_state.old_eecd, E1000State),
1489 VMSTATE_UINT8(mig_props.ipcss, E1000State),
1490 VMSTATE_UINT8(mig_props.ipcso, E1000State),
1491 VMSTATE_UINT16(mig_props.ipcse, E1000State),
1492 VMSTATE_UINT8(mig_props.tucss, E1000State),
1493 VMSTATE_UINT8(mig_props.tucso, E1000State),
1494 VMSTATE_UINT16(mig_props.tucse, E1000State),
1495 VMSTATE_UINT32(mig_props.paylen, E1000State),
1496 VMSTATE_UINT8(mig_props.hdr_len, E1000State),
1497 VMSTATE_UINT16(mig_props.mss, E1000State),
1498 VMSTATE_UINT16(tx.size, E1000State),
1499 VMSTATE_UINT16(tx.tso_frames, E1000State),
1500 VMSTATE_UINT8(tx.sum_needed, E1000State),
1501 VMSTATE_INT8(mig_props.ip, E1000State),
1502 VMSTATE_INT8(mig_props.tcp, E1000State),
1503 VMSTATE_BUFFER(tx.header, E1000State),
1504 VMSTATE_BUFFER(tx.data, E1000State),
1505 VMSTATE_UINT16_ARRAY(eeprom_data, E1000State, 64),
1506 VMSTATE_UINT16_ARRAY(phy_reg, E1000State, 0x20),
1507 VMSTATE_UINT32(mac_reg[CTRL], E1000State),
1508 VMSTATE_UINT32(mac_reg[EECD], E1000State),
1509 VMSTATE_UINT32(mac_reg[EERD], E1000State),
1510 VMSTATE_UINT32(mac_reg[GPRC], E1000State),
1511 VMSTATE_UINT32(mac_reg[GPTC], E1000State),
1512 VMSTATE_UINT32(mac_reg[ICR], E1000State),
1513 VMSTATE_UINT32(mac_reg[ICS], E1000State),
1514 VMSTATE_UINT32(mac_reg[IMC], E1000State),
1515 VMSTATE_UINT32(mac_reg[IMS], E1000State),
1516 VMSTATE_UINT32(mac_reg[LEDCTL], E1000State),
1517 VMSTATE_UINT32(mac_reg[MANC], E1000State),
1518 VMSTATE_UINT32(mac_reg[MDIC], E1000State),
1519 VMSTATE_UINT32(mac_reg[MPC], E1000State),
1520 VMSTATE_UINT32(mac_reg[PBA], E1000State),
1521 VMSTATE_UINT32(mac_reg[RCTL], E1000State),
1522 VMSTATE_UINT32(mac_reg[RDBAH], E1000State),
1523 VMSTATE_UINT32(mac_reg[RDBAL], E1000State),
1524 VMSTATE_UINT32(mac_reg[RDH], E1000State),
1525 VMSTATE_UINT32(mac_reg[RDLEN], E1000State),
1526 VMSTATE_UINT32(mac_reg[RDT], E1000State),
1527 VMSTATE_UINT32(mac_reg[STATUS], E1000State),
1528 VMSTATE_UINT32(mac_reg[SWSM], E1000State),
1529 VMSTATE_UINT32(mac_reg[TCTL], E1000State),
1530 VMSTATE_UINT32(mac_reg[TDBAH], E1000State),
1531 VMSTATE_UINT32(mac_reg[TDBAL], E1000State),
1532 VMSTATE_UINT32(mac_reg[TDH], E1000State),
1533 VMSTATE_UINT32(mac_reg[TDLEN], E1000State),
1534 VMSTATE_UINT32(mac_reg[TDT], E1000State),
1535 VMSTATE_UINT32(mac_reg[TORH], E1000State),
1536 VMSTATE_UINT32(mac_reg[TORL], E1000State),
1537 VMSTATE_UINT32(mac_reg[TOTH], E1000State),
1538 VMSTATE_UINT32(mac_reg[TOTL], E1000State),
1539 VMSTATE_UINT32(mac_reg[TPR], E1000State),
1540 VMSTATE_UINT32(mac_reg[TPT], E1000State),
1541 VMSTATE_UINT32(mac_reg[TXDCTL], E1000State),
1542 VMSTATE_UINT32(mac_reg[WUFC], E1000State),
1543 VMSTATE_UINT32(mac_reg[VET], E1000State),
1544 VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, RA, 32),
1545 VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, MTA, E1000_MC_TBL_SIZE),
1546 VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, VFTA,
1576 e1000_mmio_setup(E1000State *d) in e1000_mmio_setup()
1596 E1000State *d = E1000(dev); in pci_e1000_uninit()
1616 E1000State *s = E1000(pci_dev); in e1000_write_config()
1629 E1000State *d = E1000(pci_dev); in pci_e1000_realize()
1670 DEFINE_NIC_PROPERTIES(E1000State, conf),
1671 DEFINE_PROP_BIT("migrate_tso_props", E1000State,
1673 DEFINE_PROP_BIT("init-vet", E1000State,
1709 E1000State *n = E1000(obj); in e1000_instance_init()
1718 .instance_size = sizeof(E1000State),