Lines Matching +full:0 +full:x1e8
40 #define CADENCE_GEM_ERR_DEBUG 0
46 } while (0)
48 REG32(NWCTRL, 0x0) /* Network Control reg */
49 FIELD(NWCTRL, LOOPBACK , 0, 1)
81 REG32(NWCFG, 0x4) /* Network Config reg */
82 FIELD(NWCFG, SPEED, 0, 1)
111 REG32(NWSTATUS, 0x8) /* Network Status reg */
112 REG32(USERIO, 0xc) /* User IO reg */
114 REG32(DMACFG, 0x10) /* DMA Control reg */
131 FIELD(DMACFG, AMBA_BURST_LEN , 0, 5)
134 REG32(TXSTATUS, 0x14) /* TX Status reg */
147 FIELD(TXSTATUS, USED_BIT_READ, 0, 1)
149 REG32(RXQBASE, 0x18) /* RX Q Base address reg */
150 REG32(TXQBASE, 0x1c) /* TX Q Base address reg */
151 REG32(RXSTATUS, 0x20) /* RX Status reg */
157 FIELD(RXSTATUS, BUF_NOT_AVAILABLE, 0, 1)
159 REG32(ISR, 0x24) /* Interrupt Status reg */
191 FIELD(ISR, MGNT_FRAME_SENT, 0, 1)
192 REG32(IER, 0x28) /* Interrupt Enable reg */
193 REG32(IDR, 0x2c) /* Interrupt Disable reg */
194 REG32(IMR, 0x30) /* Interrupt Mask reg */
196 REG32(PHYMNTNC, 0x34) /* Phy Maintenance reg */
197 FIELD(PHYMNTNC, DATA, 0, 16)
202 #define MDIO_OP_READ 0x2
203 #define MDIO_OP_WRITE 0x1
205 REG32(RXPAUSE, 0x38) /* RX Pause Time reg */
206 REG32(TXPAUSE, 0x3c) /* TX Pause Time reg */
207 REG32(TXPARTIALSF, 0x40) /* TX Partial Store and Forward */
208 REG32(RXPARTIALSF, 0x44) /* RX Partial Store and Forward */
209 REG32(JUMBO_MAX_LEN, 0x48) /* Max Jumbo Frame Size */
210 REG32(HASHLO, 0x80) /* Hash Low address reg */
211 REG32(HASHHI, 0x84) /* Hash High address reg */
212 REG32(SPADDR1LO, 0x88) /* Specific addr 1 low reg */
213 REG32(SPADDR1HI, 0x8c) /* Specific addr 1 high reg */
214 REG32(SPADDR2LO, 0x90) /* Specific addr 2 low reg */
215 REG32(SPADDR2HI, 0x94) /* Specific addr 2 high reg */
216 REG32(SPADDR3LO, 0x98) /* Specific addr 3 low reg */
217 REG32(SPADDR3HI, 0x9c) /* Specific addr 3 high reg */
218 REG32(SPADDR4LO, 0xa0) /* Specific addr 4 low reg */
219 REG32(SPADDR4HI, 0xa4) /* Specific addr 4 high reg */
220 REG32(TIDMATCH1, 0xa8) /* Type ID1 Match reg */
221 REG32(TIDMATCH2, 0xac) /* Type ID2 Match reg */
222 REG32(TIDMATCH3, 0xb0) /* Type ID3 Match reg */
223 REG32(TIDMATCH4, 0xb4) /* Type ID4 Match reg */
224 REG32(WOLAN, 0xb8) /* Wake on LAN reg */
225 REG32(IPGSTRETCH, 0xbc) /* IPG Stretch reg */
226 REG32(SVLAN, 0xc0) /* Stacked VLAN reg */
227 REG32(MODID, 0xfc) /* Module ID reg */
228 REG32(OCTTXLO, 0x100) /* Octets transmitted Low reg */
229 REG32(OCTTXHI, 0x104) /* Octets transmitted High reg */
230 REG32(TXCNT, 0x108) /* Error-free Frames transmitted */
231 REG32(TXBCNT, 0x10c) /* Error-free Broadcast Frames */
232 REG32(TXMCNT, 0x110) /* Error-free Multicast Frame */
233 REG32(TXPAUSECNT, 0x114) /* Pause Frames Transmitted */
234 REG32(TX64CNT, 0x118) /* Error-free 64 TX */
235 REG32(TX65CNT, 0x11c) /* Error-free 65-127 TX */
236 REG32(TX128CNT, 0x120) /* Error-free 128-255 TX */
237 REG32(TX256CNT, 0x124) /* Error-free 256-511 */
238 REG32(TX512CNT, 0x128) /* Error-free 512-1023 TX */
239 REG32(TX1024CNT, 0x12c) /* Error-free 1024-1518 TX */
240 REG32(TX1519CNT, 0x130) /* Error-free larger than 1519 TX */
241 REG32(TXURUNCNT, 0x134) /* TX under run error counter */
242 REG32(SINGLECOLLCNT, 0x138) /* Single Collision Frames */
243 REG32(MULTCOLLCNT, 0x13c) /* Multiple Collision Frames */
244 REG32(EXCESSCOLLCNT, 0x140) /* Excessive Collision Frames */
245 REG32(LATECOLLCNT, 0x144) /* Late Collision Frames */
246 REG32(DEFERTXCNT, 0x148) /* Deferred Transmission Frames */
247 REG32(CSENSECNT, 0x14c) /* Carrier Sense Error Counter */
248 REG32(OCTRXLO, 0x150) /* Octets Received register Low */
249 REG32(OCTRXHI, 0x154) /* Octets Received register High */
250 REG32(RXCNT, 0x158) /* Error-free Frames Received */
251 REG32(RXBROADCNT, 0x15c) /* Error-free Broadcast Frames RX */
252 REG32(RXMULTICNT, 0x160) /* Error-free Multicast Frames RX */
253 REG32(RXPAUSECNT, 0x164) /* Pause Frames Received Counter */
254 REG32(RX64CNT, 0x168) /* Error-free 64 byte Frames RX */
255 REG32(RX65CNT, 0x16c) /* Error-free 65-127B Frames RX */
256 REG32(RX128CNT, 0x170) /* Error-free 128-255B Frames RX */
257 REG32(RX256CNT, 0x174) /* Error-free 256-512B Frames RX */
258 REG32(RX512CNT, 0x178) /* Error-free 512-1023B Frames RX */
259 REG32(RX1024CNT, 0x17c) /* Error-free 1024-1518B Frames RX */
260 REG32(RX1519CNT, 0x180) /* Error-free 1519-max Frames RX */
261 REG32(RXUNDERCNT, 0x184) /* Undersize Frames Received */
262 REG32(RXOVERCNT, 0x188) /* Oversize Frames Received */
263 REG32(RXJABCNT, 0x18c) /* Jabbers Received Counter */
264 REG32(RXFCSCNT, 0x190) /* Frame Check seq. Error Counter */
265 REG32(RXLENERRCNT, 0x194) /* Length Field Error Counter */
266 REG32(RXSYMERRCNT, 0x198) /* Symbol Error Counter */
267 REG32(RXALIGNERRCNT, 0x19c) /* Alignment Error Counter */
268 REG32(RXRSCERRCNT, 0x1a0) /* Receive Resource Error Counter */
269 REG32(RXORUNCNT, 0x1a4) /* Receive Overrun Counter */
270 REG32(RXIPCSERRCNT, 0x1a8) /* IP header Checksum Err Counter */
271 REG32(RXTCPCCNT, 0x1ac) /* TCP Checksum Error Counter */
272 REG32(RXUDPCCNT, 0x1b0) /* UDP Checksum Error Counter */
274 REG32(1588S, 0x1d0) /* 1588 Timer Seconds */
275 REG32(1588NS, 0x1d4) /* 1588 Timer Nanoseconds */
276 REG32(1588ADJ, 0x1d8) /* 1588 Timer Adjust */
277 REG32(1588INC, 0x1dc) /* 1588 Timer Increment */
278 REG32(PTPETXS, 0x1e0) /* PTP Event Frame Transmitted (s) */
279 REG32(PTPETXNS, 0x1e4) /* PTP Event Frame Transmitted (ns) */
280 REG32(PTPERXS, 0x1e8) /* PTP Event Frame Received (s) */
281 REG32(PTPERXNS, 0x1ec) /* PTP Event Frame Received (ns) */
282 REG32(PTPPTXS, 0x1e0) /* PTP Peer Frame Transmitted (s) */
283 REG32(PTPPTXNS, 0x1e4) /* PTP Peer Frame Transmitted (ns) */
284 REG32(PTPPRXS, 0x1e8) /* PTP Peer Frame Received (s) */
285 REG32(PTPPRXNS, 0x1ec) /* PTP Peer Frame Received (ns) */
288 REG32(DESCONF, 0x280)
289 REG32(DESCONF2, 0x284)
290 REG32(DESCONF3, 0x288)
291 REG32(DESCONF4, 0x28c)
292 REG32(DESCONF5, 0x290)
293 REG32(DESCONF6, 0x294)
295 REG32(DESCONF7, 0x298)
297 REG32(INT_Q1_STATUS, 0x400)
298 REG32(INT_Q1_MASK, 0x640)
300 REG32(TRANSMIT_Q1_PTR, 0x440)
301 REG32(TRANSMIT_Q7_PTR, 0x458)
303 REG32(RECEIVE_Q1_PTR, 0x480)
304 REG32(RECEIVE_Q7_PTR, 0x498)
306 REG32(TBQPH, 0x4c8)
307 REG32(RBQPH, 0x4d4)
309 REG32(INT_Q1_ENABLE, 0x600)
310 REG32(INT_Q7_ENABLE, 0x618)
312 REG32(INT_Q1_DISABLE, 0x620)
313 REG32(INT_Q7_DISABLE, 0x638)
315 REG32(SCREENING_TYPE1_REG0, 0x500)
316 FIELD(SCREENING_TYPE1_REG0, QUEUE_NUM, 0, 4)
323 REG32(SCREENING_TYPE2_REG0, 0x540)
324 FIELD(SCREENING_TYPE2_REG0, QUEUE_NUM, 0, 4)
337 REG32(SCREENING_TYPE2_ETHERTYPE_REG0, 0x6e0)
339 REG32(TYPE2_COMPARE_0_WORD_0, 0x700)
340 FIELD(TYPE2_COMPARE_0_WORD_0, MASK_VALUE, 0, 16)
343 REG32(TYPE2_COMPARE_0_WORD_1, 0x704)
344 FIELD(TYPE2_COMPARE_0_WORD_1, OFFSET_VALUE, 0, 7)
354 #define BOARD_PHY_ADDRESS 0 /* PHY address we will emulate a device at */
356 #define PHY_REG_CONTROL 0
381 #define PHY_REG_CONTROL_RST 0x8000
382 #define PHY_REG_CONTROL_LOOP 0x4000
383 #define PHY_REG_CONTROL_ANEG 0x1000
384 #define PHY_REG_CONTROL_ANRESTART 0x0200
386 #define PHY_REG_STATUS_LINK 0x0004
387 #define PHY_REG_STATUS_ANEGCMPL 0x0020
389 #define PHY_REG_INT_ST_ANEGCMPL 0x0800
390 #define PHY_REG_INT_ST_LINKC 0x0400
391 #define PHY_REG_INT_ST_ENERGY 0x0010
400 #define GEM_RX_SAR_ACCEPT 0
404 #define DESC_1_USED 0x80000000
405 #define DESC_1_LENGTH 0x00001FFF
407 #define DESC_1_TX_WRAP 0x40000000
408 #define DESC_1_TX_LAST 0x00008000
410 #define DESC_0_RX_WRAP 0x00000002
411 #define DESC_0_RX_OWNERSHIP 0x00000001
420 #define DESC_1_RX_SOF 0x00004000
421 #define DESC_1_RX_EOF 0x00008000
423 #define GEM_MODID_VALUE 0x00020118
427 uint64_t ret = desc[0]; in tx_desc_get_buffer()
437 return (desc[1] & DESC_1_USED) ? 1 : 0; in tx_desc_get_used()
447 return (desc[1] & DESC_1_TX_WRAP) ? 1 : 0; in tx_desc_get_wrap()
452 return (desc[1] & DESC_1_TX_LAST) ? 1 : 0; in tx_desc_get_last()
463 DB_PRINT("bufaddr: 0x%08x\n", *desc); in print_gem_tx_desc()
472 uint64_t ret = desc[0] & ~0x3UL; in rx_desc_get_buffer()
498 return desc[0] & DESC_0_RX_WRAP ? 1 : 0; in rx_desc_get_wrap()
503 return desc[0] & DESC_0_RX_OWNERSHIP ? 1 : 0; in rx_desc_get_ownership()
508 desc[0] |= DESC_0_RX_OWNERSHIP; in rx_desc_set_ownership()
518 desc[1] = 0; in rx_desc_clear_control()
554 /* The broadcast MAC address: 0xFFFFFFFFFFFF */
555 static const uint8_t broadcast_addr[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
565 " greater than 0x%" PRIx32 "\n", s->jumbo_max_len); in gem_get_max_buf_len()
578 if (q == 0) { in gem_set_isr()
595 memset(&s->regs_ro[0], 0, sizeof(s->regs_ro)); in gem_init_register_masks()
596 s->regs_ro[R_NWCTRL] = 0xFFF80000; in gem_init_register_masks()
597 s->regs_ro[R_NWSTATUS] = 0xFFFFFFFF; in gem_init_register_masks()
598 s->regs_ro[R_DMACFG] = 0x8E00F000; in gem_init_register_masks()
599 s->regs_ro[R_TXSTATUS] = 0xFFFFFE08; in gem_init_register_masks()
600 s->regs_ro[R_RXQBASE] = 0x00000003; in gem_init_register_masks()
601 s->regs_ro[R_TXQBASE] = 0x00000003; in gem_init_register_masks()
602 s->regs_ro[R_RXSTATUS] = 0xFFFFFFF0; in gem_init_register_masks()
603 s->regs_ro[R_ISR] = 0xFFFFFFFF; in gem_init_register_masks()
604 s->regs_ro[R_IMR] = 0xFFFFFFFF; in gem_init_register_masks()
605 s->regs_ro[R_MODID] = 0xFFFFFFFF; in gem_init_register_masks()
606 for (i = 0; i < s->num_priority_queues; i++) { in gem_init_register_masks()
607 s->regs_ro[R_INT_Q1_STATUS + i] = 0xFFFFFFFF; in gem_init_register_masks()
608 s->regs_ro[R_INT_Q1_ENABLE + i] = 0xFFFFF319; in gem_init_register_masks()
609 s->regs_ro[R_INT_Q1_DISABLE + i] = 0xFFFFF319; in gem_init_register_masks()
610 s->regs_ro[R_INT_Q1_MASK + i] = 0xFFFFFFFF; in gem_init_register_masks()
614 memset(&s->regs_rtc[0], 0, sizeof(s->regs_rtc)); in gem_init_register_masks()
615 s->regs_rtc[R_ISR] = 0xFFFFFFFF; in gem_init_register_masks()
616 for (i = 0; i < s->num_priority_queues; i++) { in gem_init_register_masks()
617 s->regs_rtc[R_INT_Q1_STATUS + i] = 0x00000CE6; in gem_init_register_masks()
621 memset(&s->regs_w1c[0], 0, sizeof(s->regs_w1c)); in gem_init_register_masks()
622 s->regs_w1c[R_TXSTATUS] = 0x000001F7; in gem_init_register_masks()
623 s->regs_w1c[R_RXSTATUS] = 0x0000000F; in gem_init_register_masks()
626 memset(&s->regs_wo[0], 0, sizeof(s->regs_wo)); in gem_init_register_masks()
627 s->regs_wo[R_NWCTRL] = 0x00073E60; in gem_init_register_masks()
628 s->regs_wo[R_IER] = 0x07FFFFFF; in gem_init_register_masks()
629 s->regs_wo[R_IDR] = 0x07FFFFFF; in gem_init_register_masks()
630 for (i = 0; i < s->num_priority_queues; i++) { in gem_init_register_masks()
631 s->regs_wo[R_INT_Q1_ENABLE + i] = 0x00000CE6; in gem_init_register_masks()
632 s->regs_wo[R_INT_Q1_DISABLE + i] = 0x00000CE6; in gem_init_register_masks()
674 for (i = 0; i < s->num_priority_queues; i++) { in gem_can_receive()
688 if (s->can_rx_state != 0) { in gem_can_receive()
689 s->can_rx_state = 0; in gem_can_receive()
703 qemu_set_irq(s->irq[0], !!s->regs[R_ISR]); in gem_update_int_status()
735 if (packet[0] == 0x01) { in gem_receive_updatestats()
764 byte >>= (bit & 0x7); in get_bit()
778 hash_index = 0; in calc_mac_hash()
780 for (index_bit = 5; index_bit >= 0; index_bit--) { in calc_mac_hash()
800 * >= 0: Specific address accept (which matched SAR is returned)
840 for (i = 3; i >= 0; i--) { in gem_mac_address_filter()
858 for (i = 0; i < s->num_type1_screeners; i++) { in get_queue_from_screen()
888 for (i = 0; i < s->num_type2_screeners; i++) { in get_queue_from_screen()
911 for (j = 0; j < 3; j++) { in get_queue_from_screen()
944 case 0: in get_queue_from_screen()
960 mask = 0xFFFFFFFF; in get_queue_from_screen()
981 /* We made it here, assume it's queue 0 */ in get_queue_from_screen()
982 return 0; in get_queue_from_screen()
987 uint32_t base_addr = 0; in gem_get_queue_base_addr()
990 case 0: in gem_get_queue_base_addr()
1016 hwaddr desc_addr = 0; in gem_get_desc_addr()
1040 DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", desc_addr); in gem_get_rx_desc()
1049 DB_PRINT("descriptor 0x%" HWADDR_PRIx " owned by sw.\n", desc_addr); in gem_get_rx_desc()
1069 int q = 0; in gem_receive()
1084 if (type_len < 0x600) { in gem_receive()
1093 * Determine configured receive buffer offset (probably 0) in gem_receive()
1135 memset(s->rx_packet + size, 0, MAX_FRAME_SIZE - size); in gem_receive()
1137 crc_val = cpu_to_le32(crc32(0, s->rx_packet, MAX(size, 60))); in gem_receive()
1163 DB_PRINT("copy %" PRIu32 " bytes to 0x%" PRIx64 "\n", in gem_receive()
1182 if (bytes_to_copy == 0) { in gem_receive()
1261 if (packet[0] == 0x01) { in gem_transmit_updatestats()
1292 int q = 0; in gem_transmit()
1306 total_bytes = 0; in gem_transmit()
1308 for (q = s->num_priority_queues - 1; q >= 0; q--) { in gem_transmit()
1312 DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr); in gem_transmit()
1317 while (tx_desc_get_used(desc) == 0) { in gem_transmit()
1328 if ((tx_desc_get_buffer(s, desc) == 0) || in gem_transmit()
1329 (tx_desc_get_length(desc) == 0)) { in gem_transmit()
1330 DB_PRINT("Invalid TX descriptor @ 0x%" HWADDR_PRIx "\n", in gem_transmit()
1337 qemu_log_mask(LOG_GUEST_ERROR, "TX descriptor @ 0x%" \ in gem_transmit()
1338 HWADDR_PRIx " too large: size 0x%x space 0x%zx\n", in gem_transmit()
1376 DB_PRINT("TX descriptor next: 0x%08x\n", s->tx_desc_addr[q]); in gem_transmit()
1404 total_bytes = 0; in gem_transmit()
1413 packet_desc_addr = 0; in gem_transmit()
1419 DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr); in gem_transmit()
1427 /* IRQ TXUSED is defined only for queue 0 */ in gem_transmit()
1428 if (q == 0) { in gem_transmit()
1429 gem_set_isr(s, 0, R_ISR_TX_USED_MASK); in gem_transmit()
1438 memset(&s->phy_regs[0], 0, sizeof(s->phy_regs)); in gem_phy_reset()
1439 s->phy_regs[PHY_REG_CONTROL] = 0x1140; in gem_phy_reset()
1440 s->phy_regs[PHY_REG_STATUS] = 0x7969; in gem_phy_reset()
1441 s->phy_regs[PHY_REG_PHYID1] = 0x0141; in gem_phy_reset()
1442 s->phy_regs[PHY_REG_PHYID2] = 0x0CC2; in gem_phy_reset()
1443 s->phy_regs[PHY_REG_ANEGADV] = 0x01E1; in gem_phy_reset()
1444 s->phy_regs[PHY_REG_LINKPABIL] = 0xCDE1; in gem_phy_reset()
1445 s->phy_regs[PHY_REG_ANEGEXP] = 0x000F; in gem_phy_reset()
1446 s->phy_regs[PHY_REG_NEXTP] = 0x2001; in gem_phy_reset()
1447 s->phy_regs[PHY_REG_LINKPNEXTP] = 0x40E6; in gem_phy_reset()
1448 s->phy_regs[PHY_REG_100BTCTRL] = 0x0300; in gem_phy_reset()
1449 s->phy_regs[PHY_REG_1000BTSTAT] = 0x7C00; in gem_phy_reset()
1450 s->phy_regs[PHY_REG_EXTSTAT] = 0x3000; in gem_phy_reset()
1451 s->phy_regs[PHY_REG_PHYSPCFC_CTL] = 0x0078; in gem_phy_reset()
1452 s->phy_regs[PHY_REG_PHYSPCFC_ST] = 0x7C00; in gem_phy_reset()
1453 s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL] = 0x0C60; in gem_phy_reset()
1454 s->phy_regs[PHY_REG_LED] = 0x4100; in gem_phy_reset()
1455 s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL2] = 0x000A; in gem_phy_reset()
1456 s->phy_regs[PHY_REG_EXT_PHYSPCFC_ST] = 0x848B; in gem_phy_reset()
1466 uint32_t queues_mask = 0; in gem_reset()
1471 memset(&s->regs[0], 0, sizeof(s->regs)); in gem_reset()
1472 s->regs[R_NWCFG] = 0x00080000; in gem_reset()
1473 s->regs[R_NWSTATUS] = 0x00000006; in gem_reset()
1474 s->regs[R_DMACFG] = 0x00020784; in gem_reset()
1475 s->regs[R_IMR] = 0x07ffffff; in gem_reset()
1476 s->regs[R_TXPAUSE] = 0x0000ffff; in gem_reset()
1477 s->regs[R_TXPARTIALSF] = 0x000003ff; in gem_reset()
1478 s->regs[R_RXPARTIALSF] = 0x000003ff; in gem_reset()
1480 s->regs[R_DESCONF] = 0x02D00111; in gem_reset()
1481 s->regs[R_DESCONF2] = 0x2ab10000 | s->jumbo_max_len; in gem_reset()
1482 s->regs[R_DESCONF5] = 0x002f2045; in gem_reset()
1484 s->regs[R_INT_Q1_MASK] = 0x00000CE6; in gem_reset()
1493 a = &s->conf.macaddr.a[0]; in gem_reset()
1494 s->regs[R_SPADDR1LO] = a[0] | (a[1] << 8) | (a[2] << 16) | (a[3] << 24); in gem_reset()
1497 for (i = 0; i < 4; i++) { in gem_reset()
1508 DB_PRINT("reg: %d value: 0x%04x\n", reg_num, s->phy_regs[reg_num]); in gem_phy_read()
1514 DB_PRINT("reg: %d value: 0x%04x\n", reg_num, val); in gem_phy_write()
1522 s->phy_loop = 0; in gem_phy_write()
1533 s->phy_loop = 0; in gem_phy_write()
1550 s->regs[R_PHYMNTNC] = FIELD_DP32(val, PHYMNTNC, DATA, 0xffff); in gem_handle_phy_access()
1585 DB_PRINT("offset: 0x%04x read: 0x%08x\n", (unsigned)offset*4, retval); in gem_read()
1600 DB_PRINT("0x%08x\n", retval); in gem_read()
1616 DB_PRINT("offset: 0x%04x write: 0x%08x ", (unsigned)offset, (unsigned)val); in gem_write()
1634 for (i = 0; i < s->num_priority_queues; ++i) { in gem_write()
1643 for (i = 0; i < s->num_priority_queues; i++) { in gem_write()
1656 s->rx_desc_addr[0] = val; in gem_write()
1662 s->tx_desc_addr[0] = val; in gem_write()
1706 DB_PRINT("newval: 0x%08x\n", s->regs[offset]); in gem_write()
1740 if (s->num_priority_queues == 0 || in gem_realize()
1755 for (i = 0; i < s->num_priority_queues; ++i) { in gem_realize()