60     if (!bypass_source && mux->enabled && mux->divider) {  in clock_mux_update()
61         freq_multiplier = mux->divider;  in clock_mux_update()
73                                    mux->multiplier, mux->divider);  in clock_mux_update()
139         VMSTATE_UINT32(divider, RccClockMuxState),
174                                  uint32_t multiplier, uint32_t divider)  in clock_mux_set_factor()  argument
176     if (mux->multiplier == multiplier && mux->divider == divider) {  in clock_mux_set_factor()
180         mux->multiplier, multiplier, mux->divider, divider);  in clock_mux_set_factor()
183     mux->divider = divider;  in clock_mux_set_factor()
361                                     uint32_t divider)  in pll_set_channel_divider()  argument
363     if (pll->channel_divider[channel] == divider) {  in pll_set_channel_divider()
368         channel, pll->channel_divider[channel], divider);  in pll_set_channel_divider()
370     pll->channel_divider[channel] = divider;  in pll_set_channel_divider()