Lines Matching +full:reset +full:- +full:names
2 * STM32L4X5 RCC (Reset and clock control)
4 * Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr>
5 * Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr>
7 * SPDX-License-Identifier: GPL-2.0-or-later
10 * See the COPYING file in the top-level directory.
13 * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs.
28 #include "hw/qdev-clock.h"
29 #include "hw/qdev-properties.h"
30 #include "hw/qdev-properties-system.h"
44 * consider it equal to 0. This is useful during the hold phase of reset.
49 Clock *current_source = mux->srcs[mux->src]; in clock_mux_update()
60 if (!bypass_source && mux->enabled && mux->divider) { in clock_mux_update()
61 freq_multiplier = mux->divider; in clock_mux_update()
64 clk_changed |= clock_set_mul_div(mux->out, freq_multiplier, mux->multiplier); in clock_mux_update()
65 clk_changed |= clock_set(mux->out, clock_get(current_source)); in clock_mux_update()
67 clock_propagate(mux->out); in clock_mux_update()
72 trace_stm32l4x5_rcc_mux_update(mux->id, mux->src, src_freq, in clock_mux_update()
73 mux->multiplier, mux->divider); in clock_mux_update()
82 * s->backref + (sizeof(RccClockMuxState *) * update_src). in clock_mux_src_update()
85 const uint32_t update_src = backref - s->backref; in clock_mux_src_update()
87 if (update_src == s->src) { in clock_mux_src_update()
99 s->backref[i] = s; in clock_mux_init()
100 s->srcs[i] = qdev_init_clock_in(DEVICE(s), name, in clock_mux_init()
102 &s->backref[i], in clock_mux_init()
107 s->out = qdev_init_clock_out(DEVICE(s), "out"); in clock_mux_init()
113 set_clock_mux_init_info(s, s->id); in clock_mux_reset_enter()
149 rc->phases.enter = clock_mux_reset_enter; in clock_mux_class_init()
150 rc->phases.hold = clock_mux_reset_hold; in clock_mux_class_init()
151 rc->phases.exit = clock_mux_reset_exit; in clock_mux_class_init()
152 dc->vmsd = &clock_mux_vmstate; in clock_mux_class_init()
154 dc->user_creatable = false; in clock_mux_class_init()
159 if (mux->enabled == enabled) { in clock_mux_set_enable()
164 trace_stm32l4x5_rcc_mux_enable(mux->id); in clock_mux_set_enable()
166 trace_stm32l4x5_rcc_mux_disable(mux->id); in clock_mux_set_enable()
169 mux->enabled = enabled; in clock_mux_set_enable()
176 if (mux->multiplier == multiplier && mux->divider == divider) { in clock_mux_set_factor()
179 trace_stm32l4x5_rcc_mux_set_factor(mux->id, in clock_mux_set_factor()
180 mux->multiplier, multiplier, mux->divider, divider); in clock_mux_set_factor()
182 mux->multiplier = multiplier; in clock_mux_set_factor()
183 mux->divider = divider; in clock_mux_set_factor()
189 if (mux->src == src) { in clock_mux_set_source()
193 trace_stm32l4x5_rcc_mux_set_src(mux->id, mux->src, src); in clock_mux_set_source()
194 mux->src = src; in clock_mux_set_source()
201 * consider it equal to 0. This is useful during the hold phase of reset.
209 vco_freq = muldiv64(clock_get_hz(pll->in), pll->vco_multiplier, 1); in pll_update()
212 if (!pll->channel_exists[i]) { in pll_update()
216 old_channel_freq = clock_get_hz(pll->channels[i]); in pll_update()
218 !pll->enabled || in pll_update()
219 !pll->channel_enabled[i] || in pll_update()
220 !pll->channel_divider[i]) { in pll_update()
225 pll->channel_divider[i]); in pll_update()
233 clock_update_hz(pll->channels[i], channel_freq); in pll_update()
234 trace_stm32l4x5_rcc_pll_update(pll->id, i, vco_freq, in pll_update()
250 s->in = qdev_init_clock_in(DEVICE(s), "in", in pll_init()
253 const char *names[] = { in pll_init() local
254 "out-p", "out-q", "out-r", in pll_init()
258 s->channels[i] = qdev_init_clock_out(DEVICE(s), names[i]); in pll_init()
265 set_pll_init_info(s, s->id); in pll_reset_enter()
303 rc->phases.enter = pll_reset_enter; in pll_class_init()
304 rc->phases.hold = pll_reset_hold; in pll_class_init()
305 rc->phases.exit = pll_reset_exit; in pll_class_init()
306 dc->vmsd = &pll_vmstate; in pll_class_init()
308 dc->user_creatable = false; in pll_class_init()
313 if (pll->vco_multiplier == vco_multiplier) { in pll_set_vco_multiplier()
320 __func__, vco_multiplier, pll->id); in pll_set_vco_multiplier()
324 trace_stm32l4x5_rcc_pll_set_vco_multiplier(pll->id, in pll_set_vco_multiplier()
325 pll->vco_multiplier, vco_multiplier); in pll_set_vco_multiplier()
327 pll->vco_multiplier = vco_multiplier; in pll_set_vco_multiplier()
333 if (pll->enabled == enabled) { in pll_set_enable()
337 pll->enabled = enabled; in pll_set_enable()
345 if (pll->channel_enabled[channel] == enabled) { in pll_set_channel_enable()
350 trace_stm32l4x5_rcc_pll_channel_enable(pll->id, channel); in pll_set_channel_enable()
352 trace_stm32l4x5_rcc_pll_channel_disable(pll->id, channel); in pll_set_channel_enable()
355 pll->channel_enabled[channel] = enabled; in pll_set_channel_enable()
363 if (pll->channel_divider[channel] == divider) { in pll_set_channel_divider()
367 trace_stm32l4x5_rcc_pll_set_channel_divider(pll->id, in pll_set_channel_divider()
368 channel, pll->channel_divider[channel], divider); in pll_set_channel_divider()
370 pll->channel_divider[channel] = divider; in pll_set_channel_divider()
379 if (s->cifr & CIFR_IRQ_MASK) { in rcc_update_irq()
380 qemu_irq_raise(s->irq); in rcc_update_irq()
382 qemu_irq_lower(s->irq); in rcc_update_irq()
395 val = extract32(s->cr, R_CR_MSIRGSEL_SHIFT, R_CR_MSIRGSEL_LENGTH); in rcc_update_msi()
398 val = extract32(s->cr, R_CR_MSIRANGE_SHIFT, R_CR_MSIRANGE_LENGTH); in rcc_update_msi()
401 val = extract32(s->csr, R_CSR_MSISRANGE_SHIFT, R_CSR_MSISRANGE_LENGTH); in rcc_update_msi()
405 clock_update_hz(s->msi_rc, msirange[val]); in rcc_update_msi()
411 s->cr = (s->cr & ~R_CSR_MSISRANGE_MASK) | in rcc_update_msi()
417 * TODO: Add write-protection for all registers:
426 s->clock_muxes[RCC_CLOCK_MUX_PLL_INPUT].src]; in rcc_update_cr_register()
429 val = FIELD_EX32(s->cr, CR, PLLSAI2ON); in rcc_update_cr_register()
430 pll_set_enable(&s->plls[RCC_PLL_PLLSAI2], val); in rcc_update_cr_register()
431 s->cr = (s->cr & ~R_CR_PLLSAI2RDY_MASK) | in rcc_update_cr_register()
433 if (s->cier & R_CIER_PLLSAI2RDYIE_MASK) { in rcc_update_cr_register()
434 s->cifr |= R_CIFR_PLLSAI2RDYF_MASK; in rcc_update_cr_register()
438 val = FIELD_EX32(s->cr, CR, PLLSAI1ON); in rcc_update_cr_register()
439 pll_set_enable(&s->plls[RCC_PLL_PLLSAI1], val); in rcc_update_cr_register()
440 s->cr = (s->cr & ~R_CR_PLLSAI1RDY_MASK) | in rcc_update_cr_register()
442 if (s->cier & R_CIER_PLLSAI1RDYIE_MASK) { in rcc_update_cr_register()
443 s->cifr |= R_CIFR_PLLSAI1RDYF_MASK; in rcc_update_cr_register()
448 * PLLON cannot be reset if the PLL clock is used as the system clock. in rcc_update_cr_register()
450 val = FIELD_EX32(s->cr, CR, PLLON); in rcc_update_cr_register()
451 if (FIELD_EX32(s->cfgr, CFGR, SWS) != 0b11) { in rcc_update_cr_register()
452 pll_set_enable(&s->plls[RCC_PLL_PLL], val); in rcc_update_cr_register()
453 s->cr = (s->cr & ~R_CR_PLLRDY_MASK) | in rcc_update_cr_register()
455 if (s->cier & R_CIER_PLLRDYIE_MASK) { in rcc_update_cr_register()
456 s->cifr |= R_CIFR_PLLRDYF_MASK; in rcc_update_cr_register()
459 s->cr |= R_CR_PLLON_MASK; in rcc_update_cr_register()
467 * HSEON cannot be reset if the HSE oscillator is used directly or in rcc_update_cr_register()
470 val = FIELD_EX32(s->cr, CR, HSEON); in rcc_update_cr_register()
471 if (FIELD_EX32(s->cfgr, CFGR, SWS) != 0b10 && in rcc_update_cr_register()
473 s->cr = (s->cr & ~R_CR_HSERDY_MASK) | in rcc_update_cr_register()
476 clock_update_hz(s->hse, s->hse_frequency); in rcc_update_cr_register()
477 if (s->cier & R_CIER_HSERDYIE_MASK) { in rcc_update_cr_register()
478 s->cifr |= R_CIFR_HSERDYF_MASK; in rcc_update_cr_register()
481 clock_update(s->hse, 0); in rcc_update_cr_register()
484 s->cr |= R_CR_HSEON_MASK; in rcc_update_cr_register()
495 if (FIELD_EX32(s->cfgr, CFGR, SWS) == 0b01 || in rcc_update_cr_register()
497 s->cr |= (R_CR_HSION_MASK | R_CR_HSIRDY_MASK); in rcc_update_cr_register()
498 clock_update_hz(s->hsi16_rc, HSI_FRQ); in rcc_update_cr_register()
499 if (s->cier & R_CIER_HSIRDYIE_MASK) { in rcc_update_cr_register()
500 s->cifr |= R_CIFR_HSIRDYF_MASK; in rcc_update_cr_register()
503 val = FIELD_EX32(s->cr, CR, HSION); in rcc_update_cr_register()
505 clock_update_hz(s->hsi16_rc, HSI_FRQ); in rcc_update_cr_register()
506 s->cr |= R_CR_HSIRDY_MASK; in rcc_update_cr_register()
507 if (s->cier & R_CIER_HSIRDYIE_MASK) { in rcc_update_cr_register()
508 s->cifr |= R_CIFR_HSIRDYF_MASK; in rcc_update_cr_register()
511 clock_update(s->hsi16_rc, 0); in rcc_update_cr_register()
512 s->cr &= ~R_CR_HSIRDY_MASK; in rcc_update_cr_register()
522 if (FIELD_EX32(s->cfgr, CFGR, SWS) == 0b00 || in rcc_update_cr_register()
524 s->cr |= (R_CR_MSION_MASK | R_CR_MSIRDY_MASK); in rcc_update_cr_register()
525 if (!(previous_value & R_CR_MSION_MASK) && (s->cier & R_CIER_MSIRDYIE_MASK)) { in rcc_update_cr_register()
526 s->cifr |= R_CIFR_MSIRDYF_MASK; in rcc_update_cr_register()
530 val = FIELD_EX32(s->cr, CR, MSION); in rcc_update_cr_register()
532 s->cr |= R_CR_MSIRDY_MASK; in rcc_update_cr_register()
534 if (s->cier & R_CIER_MSIRDYIE_MASK) { in rcc_update_cr_register()
535 s->cifr |= R_CIFR_MSIRDYF_MASK; in rcc_update_cr_register()
538 s->cr &= ~R_CR_MSIRDY_MASK; in rcc_update_cr_register()
539 clock_update(s->msi_rc, 0); in rcc_update_cr_register()
549 val = FIELD_EX32(s->cfgr, CFGR, MCOPRE); in rcc_update_cfgr_register()
554 clock_mux_set_enable(&s->clock_muxes[RCC_CLOCK_MUX_MCO], false); in rcc_update_cfgr_register()
556 clock_mux_set_factor(&s->clock_muxes[RCC_CLOCK_MUX_MCO], in rcc_update_cfgr_register()
561 val = FIELD_EX32(s->cfgr, CFGR, MCOSEL); in rcc_update_cfgr_register()
566 clock_mux_set_enable(&s->clock_muxes[RCC_CLOCK_MUX_MCO], false); in rcc_update_cfgr_register()
569 clock_mux_set_enable(&s->clock_muxes[RCC_CLOCK_MUX_MCO], false); in rcc_update_cfgr_register()
571 clock_mux_set_enable(&s->clock_muxes[RCC_CLOCK_MUX_MCO], true); in rcc_update_cfgr_register()
572 clock_mux_set_source(&s->clock_muxes[RCC_CLOCK_MUX_MCO], in rcc_update_cfgr_register()
573 val - 1); in rcc_update_cfgr_register()
581 val = FIELD_EX32(s->cfgr, CFGR, PPRE2); in rcc_update_cfgr_register()
583 clock_mux_set_factor(&s->clock_muxes[RCC_CLOCK_MUX_PCLK2], in rcc_update_cfgr_register()
586 clock_mux_set_factor(&s->clock_muxes[RCC_CLOCK_MUX_PCLK2], in rcc_update_cfgr_register()
587 1, 1 << (val - 0b11)); in rcc_update_cfgr_register()
591 val = FIELD_EX32(s->cfgr, CFGR, PPRE1); in rcc_update_cfgr_register()
593 clock_mux_set_factor(&s->clock_muxes[RCC_CLOCK_MUX_PCLK1], in rcc_update_cfgr_register()
596 clock_mux_set_factor(&s->clock_muxes[RCC_CLOCK_MUX_PCLK1], in rcc_update_cfgr_register()
597 1, 1 << (val - 0b11)); in rcc_update_cfgr_register()
601 val = FIELD_EX32(s->cfgr, CFGR, HPRE); in rcc_update_cfgr_register()
603 clock_mux_set_factor(&s->clock_muxes[RCC_CLOCK_MUX_HCLK], in rcc_update_cfgr_register()
606 clock_mux_set_factor(&s->clock_muxes[RCC_CLOCK_MUX_HCLK], in rcc_update_cfgr_register()
607 1, 1 << (val - 0b111)); in rcc_update_cfgr_register()
611 val = FIELD_EX32(s->cfgr, CFGR, SW); in rcc_update_cfgr_register()
612 clock_mux_set_source(&s->clock_muxes[RCC_CLOCK_MUX_SYSCLK], in rcc_update_cfgr_register()
614 s->cfgr &= ~R_CFGR_SWS_MASK; in rcc_update_cfgr_register()
615 s->cfgr |= val << R_CFGR_SWS_SHIFT; in rcc_update_cfgr_register()
621 clock_mux_set_enable(&s->clock_muxes[RCC_CLOCK_MUX_##_peripheral_name], \ in rcc_update_ahb1enr()
622 FIELD_EX32(s->ahb1enr, AHB1ENR, _peripheral_name##EN)) in rcc_update_ahb1enr()
637 clock_mux_set_enable(&s->clock_muxes[RCC_CLOCK_MUX_##_peripheral_name], \ in rcc_update_ahb2enr()
638 FIELD_EX32(s->ahb2enr, AHB2ENR, _peripheral_name##EN)) in rcc_update_ahb2enr()
662 clock_mux_set_enable(&s->clock_muxes[RCC_CLOCK_MUX_##_peripheral_name], \ in rcc_update_ahb3enr()
663 FIELD_EX32(s->ahb3enr, AHB3ENR, _peripheral_name##EN)) in rcc_update_ahb3enr()
674 clock_mux_set_enable(&s->clock_muxes[RCC_CLOCK_MUX_##_peripheral_name], \ in rcc_update_apb1enr()
675 FIELD_EX32(s->apb1enr1, APB1ENR1, _peripheral_name##EN)) in rcc_update_apb1enr()
677 clock_mux_set_enable(&s->clock_muxes[RCC_CLOCK_MUX_##_peripheral_name], \ in rcc_update_apb1enr()
678 FIELD_EX32(s->apb1enr2, APB1ENR2, _peripheral_name##EN)) in rcc_update_apb1enr()
720 clock_mux_set_enable(&s->clock_muxes[RCC_CLOCK_MUX_##_peripheral_name], \ in rcc_update_apb2enr()
721 FIELD_EX32(s->apb2enr, APB2ENR, _peripheral_name##EN)) in rcc_update_apb2enr()
750 reg = s->pllcfgr; in rcc_update_pllsaixcfgr()
753 reg = s->pllsai1cfgr; in rcc_update_pllsaixcfgr()
756 reg = s->pllsai2cfgr; in rcc_update_pllsaixcfgr()
770 pll_set_channel_divider(&s->plls[pll_id], RCC_PLL_COMMON_CHANNEL_P, in rcc_update_pllsaixcfgr()
773 pll_set_channel_divider(&s->plls[pll_id], RCC_PLL_COMMON_CHANNEL_P, in rcc_update_pllsaixcfgr()
780 pll_set_channel_divider(&s->plls[pll_id], RCC_PLL_COMMON_CHANNEL_R, in rcc_update_pllsaixcfgr()
785 pll_set_channel_enable(&s->plls[pll_id], RCC_PLL_COMMON_CHANNEL_R, val); in rcc_update_pllsaixcfgr()
789 pll_set_channel_divider(&s->plls[pll_id], RCC_PLL_COMMON_CHANNEL_Q, in rcc_update_pllsaixcfgr()
794 pll_set_channel_enable(&s->plls[pll_id], RCC_PLL_COMMON_CHANNEL_Q, val); in rcc_update_pllsaixcfgr()
798 pll_set_channel_enable(&s->plls[pll_id], RCC_PLL_COMMON_CHANNEL_P, val); in rcc_update_pllsaixcfgr()
802 pll_set_vco_multiplier(&s->plls[pll_id], val); in rcc_update_pllsaixcfgr()
815 val = FIELD_EX32(s->pllcfgr, PLLCFGR, PLLM); in rcc_update_pllcfgr()
816 clock_mux_set_factor(&s->clock_muxes[RCC_CLOCK_MUX_PLL_INPUT], 1, (val + 1)); in rcc_update_pllcfgr()
819 val = FIELD_EX32(s->pllcfgr, PLLCFGR, PLLSRC); in rcc_update_pllcfgr()
821 clock_mux_set_enable(&s->clock_muxes[RCC_CLOCK_MUX_PLL_INPUT], false); in rcc_update_pllcfgr()
823 clock_mux_set_source(&s->clock_muxes[RCC_CLOCK_MUX_PLL_INPUT], val - 1); in rcc_update_pllcfgr()
824 clock_mux_set_enable(&s->clock_muxes[RCC_CLOCK_MUX_PLL_INPUT], true); in rcc_update_pllcfgr()
831 clock_mux_set_source(&s->clock_muxes[RCC_CLOCK_MUX_##_peripheral_name], \ in rcc_update_ccipr()
832 FIELD_EX32(s->ccipr, CCIPR, _peripheral_name##SEL)) in rcc_update_ccipr()
860 val = FIELD_EX32(s->bdcr, BDCR, LSCOSEL); in rcc_update_bdcr()
861 clock_mux_set_source(&s->clock_muxes[RCC_CLOCK_MUX_LSCO], val); in rcc_update_bdcr()
863 val = FIELD_EX32(s->bdcr, BDCR, LSCOEN); in rcc_update_bdcr()
864 clock_mux_set_enable(&s->clock_muxes[RCC_CLOCK_MUX_LSCO], val); in rcc_update_bdcr()
872 val = FIELD_EX32(s->bdcr, BDCR, RTCEN); in rcc_update_bdcr()
873 clock_mux_set_enable(&s->clock_muxes[RCC_CLOCK_MUX_RTC], val); in rcc_update_bdcr()
875 val = FIELD_EX32(s->bdcr, BDCR, RTCSEL); in rcc_update_bdcr()
876 clock_mux_set_source(&s->clock_muxes[RCC_CLOCK_MUX_LCD_AND_RTC_COMMON], val); in rcc_update_bdcr()
883 val = FIELD_EX32(s->bdcr, BDCR, LSEON); in rcc_update_bdcr()
885 clock_update_hz(s->lse_crystal, LSE_FRQ); in rcc_update_bdcr()
886 s->bdcr |= R_BDCR_LSERDY_MASK; in rcc_update_bdcr()
887 if (s->cier & R_CIER_LSERDYIE_MASK) { in rcc_update_bdcr()
888 s->cifr |= R_CIFR_LSERDYF_MASK; in rcc_update_bdcr()
891 clock_update(s->lse_crystal, 0); in rcc_update_bdcr()
892 s->bdcr &= ~R_BDCR_LSERDY_MASK; in rcc_update_bdcr()
902 /* Reset flags: Not implemented */ in rcc_update_csr()
903 /* MSISRANGE: Not implemented after reset */ in rcc_update_csr()
906 val = FIELD_EX32(s->csr, CSR, LSION); in rcc_update_csr()
908 clock_update_hz(s->lsi_rc, LSI_FRQ); in rcc_update_csr()
909 s->csr |= R_CSR_LSIRDY_MASK; in rcc_update_csr()
910 if (s->cier & R_CIER_LSIRDYIE_MASK) { in rcc_update_csr()
911 s->cifr |= R_CIFR_LSIRDYF_MASK; in rcc_update_csr()
919 clock_update(s->lsi_rc, 0); in rcc_update_csr()
920 s->csr &= ~R_CSR_LSIRDY_MASK; in rcc_update_csr()
929 s->cr = 0x00000063; in stm32l4x5_rcc_reset_hold()
931 * Factory-programmed calibration data in stm32l4x5_rcc_reset_hold()
935 s->icscr = 0x106E0082; in stm32l4x5_rcc_reset_hold()
936 s->cfgr = 0x0; in stm32l4x5_rcc_reset_hold()
937 s->pllcfgr = 0x00001000; in stm32l4x5_rcc_reset_hold()
938 s->pllsai1cfgr = 0x00001000; in stm32l4x5_rcc_reset_hold()
939 s->pllsai2cfgr = 0x00001000; in stm32l4x5_rcc_reset_hold()
940 s->cier = 0x0; in stm32l4x5_rcc_reset_hold()
941 s->cifr = 0x0; in stm32l4x5_rcc_reset_hold()
942 s->ahb1rstr = 0x0; in stm32l4x5_rcc_reset_hold()
943 s->ahb2rstr = 0x0; in stm32l4x5_rcc_reset_hold()
944 s->ahb3rstr = 0x0; in stm32l4x5_rcc_reset_hold()
945 s->apb1rstr1 = 0x0; in stm32l4x5_rcc_reset_hold()
946 s->apb1rstr2 = 0x0; in stm32l4x5_rcc_reset_hold()
947 s->apb2rstr = 0x0; in stm32l4x5_rcc_reset_hold()
948 s->ahb1enr = 0x00000100; in stm32l4x5_rcc_reset_hold()
949 s->ahb2enr = 0x0; in stm32l4x5_rcc_reset_hold()
950 s->ahb3enr = 0x0; in stm32l4x5_rcc_reset_hold()
951 s->apb1enr1 = 0x0; in stm32l4x5_rcc_reset_hold()
952 s->apb1enr2 = 0x0; in stm32l4x5_rcc_reset_hold()
953 s->apb2enr = 0x0; in stm32l4x5_rcc_reset_hold()
954 s->ahb1smenr = 0x00011303; in stm32l4x5_rcc_reset_hold()
955 s->ahb2smenr = 0x000532FF; in stm32l4x5_rcc_reset_hold()
956 s->ahb3smenr = 0x00000101; in stm32l4x5_rcc_reset_hold()
957 s->apb1smenr1 = 0xF2FECA3F; in stm32l4x5_rcc_reset_hold()
958 s->apb1smenr2 = 0x00000025; in stm32l4x5_rcc_reset_hold()
959 s->apb2smenr = 0x01677C01; in stm32l4x5_rcc_reset_hold()
960 s->ccipr = 0x0; in stm32l4x5_rcc_reset_hold()
961 s->bdcr = 0x0; in stm32l4x5_rcc_reset_hold()
962 s->csr = 0x0C000600; in stm32l4x5_rcc_reset_hold()
973 retvalue = s->cr; in stm32l4x5_rcc_read()
976 retvalue = s->icscr; in stm32l4x5_rcc_read()
979 retvalue = s->cfgr; in stm32l4x5_rcc_read()
982 retvalue = s->pllcfgr; in stm32l4x5_rcc_read()
985 retvalue = s->pllsai1cfgr; in stm32l4x5_rcc_read()
988 retvalue = s->pllsai2cfgr; in stm32l4x5_rcc_read()
991 retvalue = s->cier; in stm32l4x5_rcc_read()
994 retvalue = s->cifr; in stm32l4x5_rcc_read()
997 /* CICR is write only, return the reset value = 0 */ in stm32l4x5_rcc_read()
1000 retvalue = s->ahb1rstr; in stm32l4x5_rcc_read()
1003 retvalue = s->ahb2rstr; in stm32l4x5_rcc_read()
1006 retvalue = s->ahb3rstr; in stm32l4x5_rcc_read()
1009 retvalue = s->apb1rstr1; in stm32l4x5_rcc_read()
1012 retvalue = s->apb1rstr2; in stm32l4x5_rcc_read()
1015 retvalue = s->apb2rstr; in stm32l4x5_rcc_read()
1018 retvalue = s->ahb1enr; in stm32l4x5_rcc_read()
1021 retvalue = s->ahb2enr; in stm32l4x5_rcc_read()
1024 retvalue = s->ahb3enr; in stm32l4x5_rcc_read()
1027 retvalue = s->apb1enr1; in stm32l4x5_rcc_read()
1030 retvalue = s->apb1enr2; in stm32l4x5_rcc_read()
1033 retvalue = s->apb2enr; in stm32l4x5_rcc_read()
1036 retvalue = s->ahb1smenr; in stm32l4x5_rcc_read()
1039 retvalue = s->ahb2smenr; in stm32l4x5_rcc_read()
1042 retvalue = s->ahb3smenr; in stm32l4x5_rcc_read()
1045 retvalue = s->apb1smenr1; in stm32l4x5_rcc_read()
1048 retvalue = s->apb1smenr2; in stm32l4x5_rcc_read()
1051 retvalue = s->apb2smenr; in stm32l4x5_rcc_read()
1054 retvalue = s->ccipr; in stm32l4x5_rcc_read()
1057 retvalue = s->bdcr; in stm32l4x5_rcc_read()
1060 retvalue = s->csr; in stm32l4x5_rcc_read()
1084 previous_value = s->cr; in stm32l4x5_rcc_write()
1085 s->cr = (s->cr & CR_READ_SET_MASK) | in stm32l4x5_rcc_write()
1090 s->icscr = value & ~ICSCR_READ_ONLY_MASK; in stm32l4x5_rcc_write()
1092 "%s: Side-effects not implemented for ICSCR\n", __func__); in stm32l4x5_rcc_write()
1095 s->cfgr = value & ~CFGR_READ_ONLY_MASK; in stm32l4x5_rcc_write()
1099 s->pllcfgr = value; in stm32l4x5_rcc_write()
1103 s->pllsai1cfgr = value; in stm32l4x5_rcc_write()
1107 s->pllsai2cfgr = value; in stm32l4x5_rcc_write()
1111 s->cier = value; in stm32l4x5_rcc_write()
1113 "%s: Side-effects not implemented for CIER\n", __func__); in stm32l4x5_rcc_write()
1117 "%s: Write attempt into read-only register (CIFR) 0x%"PRIx32"\n", in stm32l4x5_rcc_write()
1122 s->cifr &= ~value; in stm32l4x5_rcc_write()
1125 /* Reset behaviors are not implemented */ in stm32l4x5_rcc_write()
1127 s->ahb1rstr = value; in stm32l4x5_rcc_write()
1129 "%s: Side-effects not implemented for AHB1RSTR\n", __func__); in stm32l4x5_rcc_write()
1132 s->ahb2rstr = value; in stm32l4x5_rcc_write()
1134 "%s: Side-effects not implemented for AHB2RSTR\n", __func__); in stm32l4x5_rcc_write()
1137 s->ahb3rstr = value; in stm32l4x5_rcc_write()
1139 "%s: Side-effects not implemented for AHB3RSTR\n", __func__); in stm32l4x5_rcc_write()
1142 s->apb1rstr1 = value; in stm32l4x5_rcc_write()
1144 "%s: Side-effects not implemented for APB1RSTR1\n", __func__); in stm32l4x5_rcc_write()
1147 s->apb1rstr2 = value; in stm32l4x5_rcc_write()
1149 "%s: Side-effects not implemented for APB1RSTR2\n", __func__); in stm32l4x5_rcc_write()
1152 s->apb2rstr = value; in stm32l4x5_rcc_write()
1154 "%s: Side-effects not implemented for APB2RSTR\n", __func__); in stm32l4x5_rcc_write()
1157 s->ahb1enr = value; in stm32l4x5_rcc_write()
1161 s->ahb2enr = value; in stm32l4x5_rcc_write()
1165 s->ahb3enr = value; in stm32l4x5_rcc_write()
1169 s->apb1enr1 = value; in stm32l4x5_rcc_write()
1173 s->apb1enr2 = value; in stm32l4x5_rcc_write()
1177 s->apb2enr = (s->apb2enr & APB2ENR_READ_SET_MASK) | value; in stm32l4x5_rcc_write()
1182 s->ahb1smenr = value; in stm32l4x5_rcc_write()
1184 "%s: Side-effects not implemented for AHB1SMENR\n", __func__); in stm32l4x5_rcc_write()
1187 s->ahb2smenr = value; in stm32l4x5_rcc_write()
1189 "%s: Side-effects not implemented for AHB2SMENR\n", __func__); in stm32l4x5_rcc_write()
1192 s->ahb3smenr = value; in stm32l4x5_rcc_write()
1194 "%s: Side-effects not implemented for AHB3SMENR\n", __func__); in stm32l4x5_rcc_write()
1197 s->apb1smenr1 = value; in stm32l4x5_rcc_write()
1199 "%s: Side-effects not implemented for APB1SMENR1\n", __func__); in stm32l4x5_rcc_write()
1202 s->apb1smenr2 = value; in stm32l4x5_rcc_write()
1204 "%s: Side-effects not implemented for APB1SMENR2\n", __func__); in stm32l4x5_rcc_write()
1207 s->apb2smenr = value; in stm32l4x5_rcc_write()
1209 "%s: Side-effects not implemented for APB2SMENR\n", __func__); in stm32l4x5_rcc_write()
1212 s->ccipr = value; in stm32l4x5_rcc_write()
1216 s->bdcr = value & ~BDCR_READ_ONLY_MASK; in stm32l4x5_rcc_write()
1220 s->csr = value & ~CSR_READ_ONLY_MASK; in stm32l4x5_rcc_write()
1262 sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); in stm32l4x5_rcc_init()
1264 memory_region_init_io(&s->mmio, obj, &stm32l4x5_rcc_ops, s, in stm32l4x5_rcc_init()
1266 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); in stm32l4x5_rcc_init()
1272 &s->plls[i], TYPE_RCC_PLL); in stm32l4x5_rcc_init()
1273 set_pll_init_info(&s->plls[i], i); in stm32l4x5_rcc_init()
1280 &s->clock_muxes[i], in stm32l4x5_rcc_init()
1282 set_clock_mux_init_info(&s->clock_muxes[i], i); in stm32l4x5_rcc_init()
1286 alias = g_strdup_printf("%s-out", CLOCK_MUX_INIT_INFO[i].name); in stm32l4x5_rcc_init()
1287 qdev_alias_clock(DEVICE(&s->clock_muxes[i]), "out", DEVICE(obj), alias); in stm32l4x5_rcc_init()
1292 s->gnd = clock_new(obj, "gnd"); in stm32l4x5_rcc_init()
1302 [RCC_CLOCK_MUX_SRC_GND] = s->gnd, in connect_mux_sources()
1303 [RCC_CLOCK_MUX_SRC_HSI] = s->hsi16_rc, in connect_mux_sources()
1304 [RCC_CLOCK_MUX_SRC_HSE] = s->hse, in connect_mux_sources()
1305 [RCC_CLOCK_MUX_SRC_MSI] = s->msi_rc, in connect_mux_sources()
1306 [RCC_CLOCK_MUX_SRC_LSI] = s->lsi_rc, in connect_mux_sources()
1307 [RCC_CLOCK_MUX_SRC_LSE] = s->lse_crystal, in connect_mux_sources()
1308 [RCC_CLOCK_MUX_SRC_SAI1_EXTCLK] = s->sai1_extclk, in connect_mux_sources()
1309 [RCC_CLOCK_MUX_SRC_SAI2_EXTCLK] = s->sai2_extclk, in connect_mux_sources()
1311 s->plls[RCC_PLL_PLL].channels[RCC_PLL_CHANNEL_PLLCLK], in connect_mux_sources()
1313 s->plls[RCC_PLL_PLLSAI1].channels[RCC_PLLSAI1_CHANNEL_PLLSAI1CLK], in connect_mux_sources()
1315 s->plls[RCC_PLL_PLLSAI2].channels[RCC_PLLSAI2_CHANNEL_PLLSAI2CLK], in connect_mux_sources()
1317 s->plls[RCC_PLL_PLL].channels[RCC_PLL_CHANNEL_PLLSAI3CLK], in connect_mux_sources()
1319 s->plls[RCC_PLL_PLL].channels[RCC_PLL_CHANNEL_PLL48M1CLK], in connect_mux_sources()
1321 s->plls[RCC_PLL_PLLSAI1].channels[RCC_PLLSAI1_CHANNEL_PLL48M2CLK], in connect_mux_sources()
1323 s->plls[RCC_PLL_PLLSAI1].channels[RCC_PLLSAI1_CHANNEL_PLLADC1CLK], in connect_mux_sources()
1325 s->plls[RCC_PLL_PLLSAI2] .channels[RCC_PLLSAI2_CHANNEL_PLLADC2CLK], in connect_mux_sources()
1326 [RCC_CLOCK_MUX_SRC_SYSCLK] = s->clock_muxes[RCC_CLOCK_MUX_SYSCLK].out, in connect_mux_sources()
1327 [RCC_CLOCK_MUX_SRC_HCLK] = s->clock_muxes[RCC_CLOCK_MUX_HCLK].out, in connect_mux_sources()
1328 [RCC_CLOCK_MUX_SRC_PCLK1] = s->clock_muxes[RCC_CLOCK_MUX_PCLK1].out, in connect_mux_sources()
1329 [RCC_CLOCK_MUX_SRC_PCLK2] = s->clock_muxes[RCC_CLOCK_MUX_PCLK2].out, in connect_mux_sources()
1330 [RCC_CLOCK_MUX_SRC_HSE_OVER_32] = s->clock_muxes[RCC_CLOCK_MUX_HSE_OVER_32].out, in connect_mux_sources()
1332 s->clock_muxes[RCC_CLOCK_MUX_LCD_AND_RTC_COMMON].out, in connect_mux_sources()
1339 clock_set_source(mux->srcs[i], CLK_SRC_MAPPING[mapping]); in connect_mux_sources()
1395 if (s->hse_frequency < 4000000ULL || in stm32l4x5_rcc_realize()
1396 s->hse_frequency > 48000000ULL) { in stm32l4x5_rcc_realize()
1398 "HSE frequency is outside of the allowed [4-48]Mhz range: %" PRIx64 "", in stm32l4x5_rcc_realize()
1399 s->hse_frequency); in stm32l4x5_rcc_realize()
1404 RccPllState *pll = &s->plls[i]; in stm32l4x5_rcc_realize()
1406 clock_set_source(pll->in, s->clock_muxes[RCC_CLOCK_MUX_PLL_INPUT].out); in stm32l4x5_rcc_realize()
1414 RccClockMuxState *clock_mux = &s->clock_muxes[i]; in stm32l4x5_rcc_realize()
1427 clock_update_hz(s->msi_rc, MSI_DEFAULT_FRQ); in stm32l4x5_rcc_realize()
1428 clock_update_hz(s->sai1_extclk, s->sai1_extclk_frequency); in stm32l4x5_rcc_realize()
1429 clock_update_hz(s->sai2_extclk, s->sai2_extclk_frequency); in stm32l4x5_rcc_realize()
1430 clock_update(s->gnd, 0); in stm32l4x5_rcc_realize()
1449 rc->phases.hold = stm32l4x5_rcc_reset_hold; in stm32l4x5_rcc_class_init()
1451 dc->realize = stm32l4x5_rcc_realize; in stm32l4x5_rcc_class_init()
1452 dc->vmsd = &vmstate_stm32l4x5_rcc; in stm32l4x5_rcc_class_init()