50 #define IOTEST_DATAMATCH 0xFA
51 #define IOTEST_NOMATCH   0xCE
109     test->hdr->count = 0;  in OBJECT_DECLARE_SIMPLE_TYPE()
111         return 0;  in OBJECT_DECLARE_SIMPLE_TYPE()
120     return 0;  in OBJECT_DECLARE_SIMPLE_TYPE()
167         if (r < 0) {  in pci_testdev_write()
173     if (d->current < 0) {  in pci_testdev_write()
195     if (d->current < 0) {  in pci_testdev_read()
196         return 0;  in pci_testdev_read()
201         return 0;  in pci_testdev_read()
213     pci_testdev_write(opaque, addr, val, size, 0);  in pci_testdev_mmio_write()
252     pci_conf[PCI_INTERRUPT_PIN] = 0; /* no interrupt pin */  in pci_testdev_realize()
258     pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio);  in pci_testdev_realize()
279     for (i = 0; i < IOTEST_MAX; ++i) {  in pci_testdev_realize()
289             test->size = 0;  in pci_testdev_realize()
301         r = event_notifier_init(&test->notifier, 0);  in pci_testdev_realize()
302         assert(r >= 0);  in pci_testdev_realize()
314     for (i = 0; i < IOTEST_MAX; ++i) {  in pci_testdev_uninit()
330     DEFINE_PROP_SIZE("membar", PCITestDevState, membar_size, 0),
343     k->revision = 0x00;  in pci_testdev_class_init()