Lines Matching +full:power +full:- +full:domain
21 #include "hw/qdev-clock.h"
23 #include "qemu/error-report.h"
38 #define NPCM7XX_CLK_WDRCR_CA9C BIT(0) /* Cortex-A9 Cores */
131 * All are loaded on power-up reset. CLKENx and SWRSTR should also be loaded on
132 * core domain reset, but this reset type is not yet supported by QEMU.
201 #define TYPE_NPCM7XX_CLOCK_PLL "npcm7xx-clock-pll"
204 #define TYPE_NPCM7XX_CLOCK_SEL "npcm7xx-clock-sel"
207 #define TYPE_NPCM7XX_CLOCK_DIVIDER "npcm7xx-clock-divider"
214 uint32_t con = s->clk->regs[s->reg]; in npcm7xx_clk_update_pll()
219 freq = clock_get_hz(s->clock_in); in npcm7xx_clk_update_pll()
226 clock_update_hz(s->clock_out, freq); in npcm7xx_clk_update_pll()
232 uint32_t index = extract32(s->clk->regs[NPCM7XX_CLK_CLKSEL], s->offset, in npcm7xx_clk_update_sel()
233 s->len); in npcm7xx_clk_update_sel()
235 if (index >= s->input_size) { in npcm7xx_clk_update_sel()
241 clock_update_hz(s->clock_out, clock_get_hz(s->clock_in[index])); in npcm7xx_clk_update_sel()
249 freq = s->divide(s); in npcm7xx_clk_update_divider()
250 clock_update_hz(s->clock_out, freq); in npcm7xx_clk_update_divider()
255 return clock_get_hz(s->clock_in) / s->divisor; in divide_by_constant()
260 return clock_get_hz(s->clock_in) / in divide_by_reg_divisor()
261 (extract32(s->clk->regs[s->reg], s->offset, s->len) + 1); in divide_by_reg_divisor()
271 return clock_get_hz(s->clock_in) >> in shift_by_reg_divisor()
272 extract32(s->clk->regs[s->reg], s->offset, s->len); in shift_by_reg_divisor()
296 npcm7xx_clk_update_pll(&clk->plls[i]); in npcm7xx_clk_update_all_plls()
305 npcm7xx_clk_update_sel(&clk->sels[i]); in npcm7xx_clk_update_all_sels()
314 npcm7xx_clk_update_divider(&clk->dividers[i]); in npcm7xx_clk_update_all_dividers()
320 clock_update_hz(clk->clkref, NPCM7XX_CLOCK_REF_HZ); in npcm7xx_clk_update_all_clocks()
395 .public_name = "pixel-clock",
406 .public_name = "mc-phy-clock",
417 .public_name = "system-clock",
492 .name = "mc-divider",
497 .public_name = "mc-clock"
500 .name = "axi-divider",
510 .name = "ahb-divider",
520 .name = "ahb3-divider",
527 .public_name = "ahb3-spi3-clock"
530 .name = "spi0-divider",
537 .public_name = "spi0-clock",
540 .name = "spix-divider",
547 .public_name = "spix-clock",
550 .name = "apb1-divider",
557 .public_name = "apb1-clock",
560 .name = "apb2-divider",
567 .public_name = "apb2-clock",
570 .name = "apb3-divider",
577 .public_name = "apb3-clock",
580 .name = "apb4-divider",
587 .public_name = "apb4-clock",
590 .name = "apb5-divider",
597 .public_name = "apb5-clock",
600 .name = "clkout-divider",
610 .name = "uart-divider",
617 .public_name = "uart-clock",
620 .name = "timer-divider",
627 .public_name = "timer-clock",
630 .name = "adc-divider",
637 .public_name = "adc-clock",
640 .name = "mmc-divider",
647 .public_name = "mmc-clock",
650 .name = "sdhc-divider",
657 .public_name = "sdhc-clock",
660 .name = "gfxm-divider",
665 .public_name = "gfxm-clock",
668 .name = "utmi-divider",
675 .public_name = "utmi-clock",
688 pll->clock_in = qdev_init_clock_in(DEVICE(pll), "clock-in", in npcm7xx_clk_pll_init()
691 pll->clock_out = qdev_init_clock_out(DEVICE(pll), "clock-out"); in npcm7xx_clk_pll_init()
705 g_autofree char *s = g_strdup_printf("clock-in[%d]", i); in npcm7xx_clk_sel_init()
706 sel->clock_in[i] = qdev_init_clock_in(DEVICE(sel), s, in npcm7xx_clk_sel_init()
709 sel->clock_out = qdev_init_clock_out(DEVICE(sel), "clock-out"); in npcm7xx_clk_sel_init()
721 div->clock_in = qdev_init_clock_in(DEVICE(div), "clock-in", in npcm7xx_clk_divider_init()
724 div->clock_out = qdev_init_clock_out(DEVICE(div), "clock-out"); in npcm7xx_clk_divider_init()
730 pll->name = init_info->name; in npcm7xx_init_clock_pll()
731 pll->clk = clk; in npcm7xx_init_clock_pll()
732 pll->reg = init_info->reg; in npcm7xx_init_clock_pll()
733 if (init_info->public_name != NULL) { in npcm7xx_init_clock_pll()
734 qdev_alias_clock(DEVICE(pll), "clock-out", DEVICE(clk), in npcm7xx_init_clock_pll()
735 init_info->public_name); in npcm7xx_init_clock_pll()
742 int input_size = init_info->input_size; in npcm7xx_init_clock_sel()
744 sel->name = init_info->name; in npcm7xx_init_clock_sel()
745 sel->clk = clk; in npcm7xx_init_clock_sel()
746 sel->input_size = init_info->input_size; in npcm7xx_init_clock_sel()
748 sel->offset = init_info->offset; in npcm7xx_init_clock_sel()
749 sel->len = init_info->len; in npcm7xx_init_clock_sel()
750 if (init_info->public_name != NULL) { in npcm7xx_init_clock_sel()
751 qdev_alias_clock(DEVICE(sel), "clock-out", DEVICE(clk), in npcm7xx_init_clock_sel()
752 init_info->public_name); in npcm7xx_init_clock_sel()
759 div->name = init_info->name; in npcm7xx_init_clock_divider()
760 div->clk = clk; in npcm7xx_init_clock_divider()
762 div->divide = init_info->divide; in npcm7xx_init_clock_divider()
763 if (div->divide == divide_by_constant) { in npcm7xx_init_clock_divider()
764 div->divisor = init_info->divisor; in npcm7xx_init_clock_divider()
766 div->reg = init_info->reg; in npcm7xx_init_clock_divider()
767 div->offset = init_info->offset; in npcm7xx_init_clock_divider()
768 div->len = init_info->len; in npcm7xx_init_clock_divider()
770 if (init_info->public_name != NULL) { in npcm7xx_init_clock_divider()
771 qdev_alias_clock(DEVICE(div), "clock-out", DEVICE(clk), in npcm7xx_init_clock_divider()
772 init_info->public_name); in npcm7xx_init_clock_divider()
781 return clk->clkref; in npcm7xx_get_clock()
783 return clk->plls[index].clock_out; in npcm7xx_get_clock()
785 return clk->sels[index].clock_out; in npcm7xx_get_clock()
787 return clk->dividers[index].clock_out; in npcm7xx_get_clock()
801 clock_set_source(clk->plls[i].clock_in, src); in npcm7xx_connect_clocks()
807 clock_set_source(clk->sels[i].clock_in[j], src); in npcm7xx_connect_clocks()
813 clock_set_source(clk->dividers[i].clock_in, src); in npcm7xx_connect_clocks()
825 if (reg >= c->nr_regs) { in npcm_clk_read()
835 "%s: register @ 0x%04" HWADDR_PRIx " is write-only\n", in npcm_clk_read()
841 value = (now_ns - s->ref_ns) / NANOSECONDS_PER_SECOND; in npcm_clk_read()
852 value = (((now_ns - s->ref_ns) / 640) << 4) % NPCM7XX_CLOCK_REF_HZ; in npcm_clk_read()
856 value = s->regs[reg]; in npcm_clk_read()
875 if (reg >= c->nr_regs) { in npcm_clk_write()
894 /* Power down -- clear lock and indicate loss of lock */ in npcm_clk_write()
898 /* Normal mode -- assume always locked */ in npcm_clk_write()
909 npcm7xx_clk_update_pll(&s->plls[find_pll_by_reg(reg)]); in npcm_clk_write()
925 "%s: register @ 0x%04" HWADDR_PRIx " is read-only\n", in npcm_clk_write()
930 s->regs[reg] = value; in npcm_clk_write()
941 rcr = clk->regs[NPCM7XX_CLK_WD0RCR + n]; in npcm7xx_clk_perform_watchdog_reset()
967 size_t sizeof_regs = c->nr_regs * sizeof(uint32_t); in npcm_clk_enter_reset()
968 g_assert(sizeof(s->regs) >= sizeof_regs); in npcm_clk_enter_reset()
969 memcpy(s->regs, c->cold_reset_values, sizeof_regs); in npcm_clk_enter_reset()
970 s->ref_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); in npcm_clk_enter_reset()
973 * A small number of registers need to be reset on a core domain reset, in npcm_clk_enter_reset()
982 s->clkref = qdev_init_clock_in(DEVICE(s), "clkref", NULL, NULL, 0); in npcm7xx_clk_init_clock_hierarchy()
991 &s->plls[i], TYPE_NPCM7XX_CLOCK_PLL); in npcm7xx_clk_init_clock_hierarchy()
992 npcm7xx_init_clock_pll(&s->plls[i], s, in npcm7xx_clk_init_clock_hierarchy()
997 &s->sels[i], TYPE_NPCM7XX_CLOCK_SEL); in npcm7xx_clk_init_clock_hierarchy()
998 npcm7xx_init_clock_sel(&s->sels[i], s, in npcm7xx_clk_init_clock_hierarchy()
1003 &s->dividers[i], TYPE_NPCM7XX_CLOCK_DIVIDER); in npcm7xx_clk_init_clock_hierarchy()
1004 npcm7xx_init_clock_divider(&s->dividers[i], s, in npcm7xx_clk_init_clock_hierarchy()
1011 clock_update_hz(s->clkref, NPCM7XX_CLOCK_REF_HZ); in npcm7xx_clk_init_clock_hierarchy()
1018 memory_region_init_io(&s->iomem, obj, &npcm_clk_ops, s, in npcm_clk_init()
1020 sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem); in npcm_clk_init()
1045 if (!qdev_realize(DEVICE(&s->plls[i]), NULL, errp)) { in npcm_clk_realize()
1050 if (!qdev_realize(DEVICE(&s->sels[i]), NULL, errp)) { in npcm_clk_realize()
1055 if (!qdev_realize(DEVICE(&s->dividers[i]), NULL, errp)) { in npcm_clk_realize()
1062 .name = "npcm7xx-clock-pll",
1072 .name = "npcm7xx-clock-sel",
1083 .name = "npcm7xx-clock-divider",
1093 .name = "npcm-clk",
1109 dc->desc = "NPCM7xx Clock PLL Module"; in npcm7xx_clk_pll_class_init()
1110 dc->vmsd = &vmstate_npcm7xx_clk_pll; in npcm7xx_clk_pll_class_init()
1112 dc->user_creatable = false; in npcm7xx_clk_pll_class_init()
1119 dc->desc = "NPCM7xx Clock SEL Module"; in npcm7xx_clk_sel_class_init()
1120 dc->vmsd = &vmstate_npcm7xx_clk_sel; in npcm7xx_clk_sel_class_init()
1122 dc->user_creatable = false; in npcm7xx_clk_sel_class_init()
1129 dc->desc = "NPCM7xx Clock Divider Module"; in npcm7xx_clk_divider_class_init()
1130 dc->vmsd = &vmstate_npcm7xx_clk_divider; in npcm7xx_clk_divider_class_init()
1132 dc->user_creatable = false; in npcm7xx_clk_divider_class_init()
1140 dc->vmsd = &vmstate_npcm_clk; in npcm_clk_class_init()
1141 dc->realize = npcm_clk_realize; in npcm_clk_class_init()
1142 rc->phases.enter = npcm_clk_enter_reset; in npcm_clk_class_init()
1150 dc->desc = "NPCM7xx Clock Control Registers"; in npcm7xx_clk_class_init()
1151 c->nr_regs = NPCM7XX_CLK_NR_REGS; in npcm7xx_clk_class_init()
1152 c->cold_reset_values = npcm7xx_cold_reset_values; in npcm7xx_clk_class_init()
1160 dc->desc = "NPCM8xx Clock Control Registers"; in npcm8xx_clk_class_init()
1161 c->nr_regs = NPCM8XX_CLK_NR_REGS; in npcm8xx_clk_class_init()
1162 c->cold_reset_values = npcm8xx_cold_reset_values; in npcm8xx_clk_class_init()