hw/misc/mac_via.c

59                                 * as CHRP on SE/30,II,IIx,IIcx,IIci.
60                                 * on IIfx, "0 means an active request"
65                                 * signal from port B of the SCC appear on
67                                 * [Macintosh Family] On the SE/30, this
70                                 * on II,IIx,IIcx,IIci,IIfx this is a bit
77                                 * state-control line SEL" on all but IIfx
80                                 * [Macintosh Family] On SE/30,II,IIx,IIcx
82                                 * map in the address decoders as it is on
85                                 * On the IIci,IIfx it is another bit of the
90                                 * on the PA7 input pin (CHRP). Output.
100                                 * [Macintosh Family] Correct on all but IIfx
105  * on Macs which had the PWM sound hardware.  Reserved on newer models.
106  * On IIci,IIfx, bits 1-2 are the rest of the CPU ID:
108  * bit 1: 1 on both IIci and IIfx.
114 #define VIA1A_CPUID0    0x02    /* CPU id bit 0 on RBV, others */
115 #define VIA1A_CPUID1    0x04    /* CPU id bit 0 on RBV, others */
116 #define VIA1A_CPUID2    0x10    /* CPU id bit 0 on RBV, others */
117 #define VIA1A_CPUID3    0x40    /* CPU id bit 0 on RBV, others */
123  * Info on VIA1B is from Macintosh Family Hardware & MkLinux.
129                                 * Also, on IIci w/parity, shows parity error
133                                 * On IIci, parity enable. 0=enabled,1=disabled
134                                 * On SE/30, vertical sync interrupt enable.
137                                 * On Quadra 800 this bit toggles A/UX mode which
142 #define VIA1B_vADBS2   0x20    /* ADB state input bit 1 (unused on IIfx) */
143 #define VIA1B_vADBS1   0x10    /* ADB state input bit 0 (unused on IIfx) */
144 #define VIA1B_vADBInt  0x08    /* ADB interrupt 0=interrupt (unused on IIfx)*/
184                                * on IIci, parity test: 0=test mode.
189                                * 0=plug is inserted.  On SE/30, always 0
195                                * on II, AMU/PMMU control.
198                                * on SE/30 tied low.
199                                * on IIx,IIcx,IIfx, unused.
200                                * on IIci/RBV, cache control. 0=flush cache.
204                               * on SE/30 this signal sent to PDS card.
208                               * on SE/30 sent to PDS card.
211                               * Cache control. On IIci, 1=disable cache card
212                               * on others, 0=disable processor's instruction
269 #define VIA1ACR_vShiftExtClk       0x0c        /* Shift on external clock */
381  * The letter a indicates bits whose value depend on what parameter
891  * speed of QEMU execution on a modern host
1053              * this situation never occurs causing a hang on boot. Use a  in mos6522_q800_via1_read()
1147          * On a Q800 an emulated VIA2 is integrated into the onboard logic. The  in mos6522_q800_via2_read()
1149          * latched as it would be on a real VIA so do the same here.  in mos6522_q800_via2_read()