27 #include "hw/qdev-properties.h"
35  * MCC (version 0, implementation 0) SS-600MP
36  * EMC (version 0, implementation 1) SS-10
37  * SMC (version 0, implementation 2) SS-10SX and SS-20
40  * "Sun-4M System Architecture (revision 2.0) by Chuck Narad", 950-1373-01,
75 #define ECC_MER_VER    0x0f000000      /* Version */
77 #define ECC_MER_MASK_0 0x00000103      /* Version 0 (MCC) mask */
78 #define ECC_MER_MASK_1 0x00000bff      /* Version 1 (EMC) mask */
79 #define ECC_MER_MASK_2 0x00000bff      /* Version 2 (SMC) mask */
102 #define ECC_MFAR0_PADDR 0x0000000f     /* PA[32-35] */
108 #define ECC_MFAR0_VADDR 0x003fc000     /* VA[12-19] (superset bits) */
127 #define ECC_DIAG_MASK  (ECC_DIAG_SIZE - 1)
139     uint32_t version;  member
149         if (s->version == ECC_MCC)  in ecc_mem_write()
150             s->regs[ECC_MER] = (val & ECC_MER_MASK_0);  in ecc_mem_write()
151         else if (s->version == ECC_EMC)  in ecc_mem_write()
152             s->regs[ECC_MER] = s->version | (val & ECC_MER_MASK_1);  in ecc_mem_write()
153         else if (s->version == ECC_SMC)  in ecc_mem_write()
154             s->regs[ECC_MER] = s->version | (val & ECC_MER_MASK_2);  in ecc_mem_write()
158         s->regs[ECC_MDR] =  val & ECC_MDR_MASK;  in ecc_mem_write()
162         s->regs[ECC_MFSR] =  val;  in ecc_mem_write()
163         qemu_irq_lower(s->irq);  in ecc_mem_write()
167         s->regs[ECC_VCR] =  val;  in ecc_mem_write()
171         s->regs[ECC_DR] =  val;  in ecc_mem_write()
175         s->regs[ECC_ECR0] =  val;  in ecc_mem_write()
179         s->regs[ECC_ECR0] =  val;  in ecc_mem_write()
193         ret = s->regs[ECC_MER];  in ecc_mem_read()
197         ret = s->regs[ECC_MDR];  in ecc_mem_read()
201         ret = s->regs[ECC_MFSR];  in ecc_mem_read()
205         ret = s->regs[ECC_VCR];  in ecc_mem_read()
209         ret = s->regs[ECC_MFAR0];  in ecc_mem_read()
213         ret = s->regs[ECC_MFAR1];  in ecc_mem_read()
217         ret = s->regs[ECC_DR];  in ecc_mem_read()
221         ret = s->regs[ECC_ECR0];  in ecc_mem_read()
225         ret = s->regs[ECC_ECR0];  in ecc_mem_read()
248     s->diag[addr & ECC_DIAG_MASK] = val;  in ecc_diag_mem_write()
255     uint32_t ret = s->diag[(int)addr];  in ecc_diag_mem_read()
278         VMSTATE_UINT32(version, ECCState),
287     if (s->version == ECC_MCC) {  in ecc_reset()
288         s->regs[ECC_MER] &= ECC_MER_REU;  in ecc_reset()
290         s->regs[ECC_MER] &= (ECC_MER_VER | ECC_MER_IMPL | ECC_MER_MRR |  in ecc_reset()
293     s->regs[ECC_MDR] = 0x20;  in ecc_reset()
294     s->regs[ECC_MFSR] = 0;  in ecc_reset()
295     s->regs[ECC_VCR] = 0;  in ecc_reset()
296     s->regs[ECC_MFAR0] = 0x07c00000;  in ecc_reset()
297     s->regs[ECC_MFAR1] = 0;  in ecc_reset()
298     s->regs[ECC_DR] = 0;  in ecc_reset()
299     s->regs[ECC_ECR0] = 0;  in ecc_reset()
300     s->regs[ECC_ECR1] = 0;  in ecc_reset()
308     sysbus_init_irq(dev, &s->irq);  in ecc_init()
310     memory_region_init_io(&s->iomem, obj, &ecc_mem_ops, s, "ecc", ECC_SIZE);  in ecc_init()
311     sysbus_init_mmio(dev, &s->iomem);  in ecc_init()
319     s->regs[0] = s->version;  in ecc_realize()
321     if (s->version == ECC_MCC) { // SS-600MP only  in ecc_realize()
322         memory_region_init_io(&s->iomem_diag, OBJECT(dev), &ecc_diag_mem_ops, s,  in ecc_realize()
324         sysbus_init_mmio(sbd, &s->iomem_diag);  in ecc_realize()
329     DEFINE_PROP_UINT32("version", ECCState, version, -1),
336     dc->realize = ecc_realize;  in ecc_class_init()
338     dc->vmsd = &vmstate_ecc;  in ecc_class_init()