Lines Matching refs:csr
117 uint32_t csr; member
311 next_state->dma[NEXTDMA_ENRX].csr |= DMA_DEV2M; in next_dma_write()
316 next_state->dma[NEXTDMA_ENRX].csr |= DMA_ENABLE; in next_dma_write()
319 next_state->dma[NEXTDMA_ENRX].csr |= DMA_SUPDATE; in next_dma_write()
322 next_state->dma[NEXTDMA_ENRX].csr &= ~DMA_COMPLETE; in next_dma_write()
326 next_state->dma[NEXTDMA_ENRX].csr &= ~(DMA_COMPLETE | DMA_SUPDATE | in next_dma_write()
346 next_state->dma[NEXTDMA_SCSI].csr |= DMA_DEV2M; in next_dma_write()
350 next_state->dma[NEXTDMA_SCSI].csr |= DMA_ENABLE; in next_dma_write()
353 next_state->dma[NEXTDMA_SCSI].csr |= DMA_SUPDATE; in next_dma_write()
356 next_state->dma[NEXTDMA_SCSI].csr &= ~DMA_COMPLETE; in next_dma_write()
360 next_state->dma[NEXTDMA_SCSI].csr &= ~(DMA_COMPLETE | DMA_SUPDATE | in next_dma_write()
400 val = next_state->dma[NEXTDMA_SCSI].csr; in next_dma_read()
404 val = next_state->dma[NEXTDMA_ENRX].csr; in next_dma_read()
601 if (!(next_state->dma[type].csr & DMA_SUPDATE)) { in nextdma_write()
607 next_state->dma[type].csr |= DMA_COMPLETE; /* DON'T CHANGE THIS! */ in nextdma_write()